I am having trouble getting triggering a GPIO interrupt on any GPIO other than GPIO_0. I started with the sample code provided by Steven Ji (http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/171824.aspx). It works great for GPIO_0 as an output. I need to capture GPIO_1 and GPIO_2 as inputs, both rising edge. Since I'm getting the GPIO_0 interrupt when I set the output, I am fairly certain I have the interrupt itself running properly, but I can't get an interrupt on the other I/O. I even tried to add GPIO_3 as an output, also triggered on rising edge, but it doesn't call the ISR either. Only GPIO_0 does.
I've checked the registers, and the "bank_registers_intstat" (in CCS) shows that my other GPIO bits are being detected, but no ISR call.
I'm using event 90 (GPINTn). Is that not the correct event number for GPIO interrups in general? Are there separate event numbers for each bit in the GPIO?
My GPIO setup code looks like this:
hGpio =CSL_GPIO_open (0);
CSL_GPIO_clearOutputData (hGpio, 0);
CSL_GPIO_setPinDirOutput (hGpio, 0);
CSL_GPIO_clearOutputData (hGpio, 3);
CSL_GPIO_setPinDirOutput (hGpio, 3);
CSL_GPIO_setPinDirInput (hGpio, 1);
CSL_GPIO_setPinDirInput (hGpio, 2);
CSL_GPIO_setRisingEdgeDetect (hGpio, 0);
CSL_GPIO_setRisingEdgeDetect (hGpio, 3);
CSL_GPIO_setRisingEdgeDetect (hGpio, 1);
CSL_GPIO_setRisingEdgeDetect (hGpio, 2);
// Enable GPIO per bank interrupt for bank 0
CSL_GPIO_bankInterruptEnable (hGpio, 0);
My interrupt setup looks like this (minus error checking on function return values):
intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 10;
CSL_intcInit (&intcContext);
CSL_intcGlobalNmiEnable ();
CSL_intcGlobalEnable (&state);
vectId =CSL_INTC_VECTID_4;
hTest = CSL_intcOpen (&intcObj, 90, &vectId, NULL);
EventRecord.handler = &intIsr;
EventRecord.arg = 0;
CSL_intcPlugEventHandler (hTest, &EventRecord);
CSL_intcHwControl (hTest, CSL_INTC_CMD_EVTENABLE, NULL);
Any help would be greatly appreciated.