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[C6678, SPI Boot] Confirming RBL behavior to configure EMIF I/F and MAIN/DDR PLL

Naoki Kawada
Guru 19890 points

Hi, 

I'm investigating, how to configure EMIF I/F and MAIN/DDR PLL with RBL, especially for SPI Boot.
I found the following post and now I prefer to embed EMIF configurations to boot application.

The following is my overall understandings about SPI boot with EMIF and MAIN/DDR PLL configurations. Is my understanding correct ?
I need to explain the boot sequence to our customer (not MAD use case). So let me clarify the details about this.

  • Create boot app and convert it to boot table. Some pre-processings discussed by the above post should be required.
  • Use romparse utility to add a boot parameter for the attached SPI NOR device to C6678's executable image and place the product into the appropriate offset address of SPI NOR.  
  • After C6678 power cycle, it gets started from RBL. First of all, RBL detects a boot parameter for SPI and configure MAIN PLL with default values (if PLL is being enabled in Common Parameters in Boot Parameter) and SPI peripheral as desired.
  • Next, RBL detects a boot table and starts to copy sections from SPI NOR to its run address.
  • During the section copy, RBL checks if a set of EMIF configurations are newly loaded to 0x00873500 (DDR configuration table, let me call it ".ddr_config_table") at the completion of each section copy.  
  • So, application must intentionally place .ddr_config_table section to 0x00873500 and .ddr_config_table section should be present at the top of boot table (strictly speaking, it is okay if before the copy sections to DDR)

Best Regards,
Kawada

  • 0
    TI__Guru** 116170 points

    Hi Kawada,

    Yes. your understanding regarding creation of the boot image and the boot process for C6678 is accurate.  On the C6678 EVM, there is an IBL flashed on the I2C EEPROM which will always run by default to correct the PLL issue we had on earlier revisions of the silicon.  Also note, the DDR configuration table for C6678 doesn`t contain DDR levelling configuration and the DDR initialization sequence was has changed slightly since the last revision of the RBL so it is recommended that you run the DDR at lower speeds while initializing it from the RBL and then speed it up  from the application initialization code.

    We have a couple of examples that we like to share for SPI_NOR that may be useful to your customer so please take a look at the reference examples to check for the implementation.

    KeystoneI_bootloader_workshop.zip

    LabKeystone_I_boot.docx

    This is an basic example to test SPI boot on C6678 with the documentation for the steps used to create the boot image.

    Regards,


    Rahul

  • 0 in reply to Rahul Prabhu
    TI__Guru** 116170 points

    SInce, we use a secondary bootloader on the EVM, we recommend initialization of the DDR from the IBL but we have an example that was created for C6657 device that shows how to use the DDR configuration table. Please note that the DDR configuration table structure and base address may be different so you will need to modify the example appropriately.


    SPIboot_ddr_modified.zip

    Hope this helps.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 19890 points
    Hi Rahul,

    Thank you for your information. Thanks to your helps and deliveries, I could understand the basics of SPI Boot.

    Now I seem embedding DDR configurations to boot application is not enough for the leveling and I'm now investigating IBL rather than this.
    Please let me ask you if I have questions about IBL with separate e2e post.

    Thanks
    Kawada