• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 104 subscribers
  • Views 2044 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6678 SPI BOOT ddr boot table

haipeng mu
Prodigy 100 points

I want to boot my application to DDR3 through SPI BOOT with the Boot Config Table, but the ddr configuration values of our board diffrent from 6678EVM. I don't know how to modify the Boot Config Table of the APP IMAGE,i hope for your help! below is the ddrtable[120] in <AddDDrTable.exe> for 6678EVM:

0x00, 0x00, 0x00, 0x70, 0x00, 0x87, 0x35, 0x00, 0x02, 0x42, 0x80, 0xF5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x02,
0x63, 0x06, 0x2A, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x50, 0x11, 0x13, 0x78, 0x3C, 0x30, 0x71, 0x7F, 0xE3, 0x55, 0x9F, 0x86, 0xAF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x70, 0x07, 0x32, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x05

  • 0
    TI__Guru** 116020 points
    Hi Haipeng mu,

    Before creating the DDR configuration table, we recommend that you create a GEL file as we do on the EVMs which initializes the DDR on your board. Once you have that you can populate the fields of the DDR configuration table based on the settings provided in the GEL file.

    The DDR configuration table has been described int he tiboot.h file that is part of the IBL code in the SDK or can be seen in the datasheet in table 2.5.3.8.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Prodigy 100 points
    Hi Rahul,
    Thanks for your reply! We have been successfully initialized the ddr3 by GELfile,and read the configuration table from the address of start at 0x2100 0008,but when I write the configuration table to 0x00873500 address(or 0x008ffd20, or0x0087fd20),the value of 0x2100 0008 address is not what i want.please,where the configuration table should be written for C6678?
  • 0 in reply to haipeng mu
    TI__Guru* 81335 points

    As the boot loader user guide suggests, the romparse utility was created to append boot parameter table and boot configuration table to the boot table. However in the current form the romparse is only used  to append boot parameter tables. For DDR configurations you will need to create a pragma DATA_Section in your main function that places the DDR configuration table in the DDR config memory space. The boot loader copies this DDR configuration table when it loads the application binary and when it notices the change in the DDR configuration memory section it will proceed to initialize DDR before loading the DDR sections of your application binary.This is demonstrated in the .bat file included in the example attached.

    7080.SPIboot_ddr.zip

    Please look at the example attached. The parameter table in the nysh.spi.map provides the modified SPI boot parameter table. The spiboot.c file and spiboot.cmd demonstrates the placement of  the DDR3 configuration table.

  • 0 in reply to Raja
    Prodigy 20 points

    HI, I cann't find the explain in pll user guide. Please show the exact formula

    3, /* pllPrediv */
    40, /* pllMult */
    2, /* pllPostDiv */

  • 0 in reply to Raja
    Prodigy 20 points

    HI, I cann't find the explain of these parameters, it's different from ddr3 pll from gel. Please show the exact formula 

    3, /* pllPrediv */
    40, /* pllMult */
    2, /* pllPostDiv */

  • 0 in reply to user3603595
    TI__Guru** 116020 points
    Yes, the parameters are different from the GEL file but the formula utilized is the same as the documentation. For C6678 and C6657 device, the DDR PLL initialization sequence was chnaged after the bootROM code was finalized and also BootROM doesn`t support many features like DDR hardware leveling, etc so our recommendation for user who want to load code in DDR is to setup a lower DDR clock using boot ROM and boot the device and then increase the DDR clock when the application boots up.

    The DDR configuration table used in the example is from a hardware platform that was using a 100 Mhz DDR Clk_in so those settings will result in setting of 666.66Mhz instead of the max supported 1333.33
    100 * 40/ (3*2) = 666.66 Mhz

    On the C6657 EVM which uses the 50Mhz clock this will result in half of that value 333.33 Mhz
    50 * 40/ (3*2) = 333.33 Mhz

    I believe this is only a example safe setting provided in the example. You can check with your DDR chips if there is any issues booting at higher clocks and determine whether the clock needs to start off at lower clock and then be increased or if you can boot reliably with higher clock value.

    Regards,
    Rahul
  • 0 in reply to Raja
    Prodigy 10 points

    your file can not be load to the ddr,

    just like a ***.