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c6678 DDR boot table in spi nor boot mode

user_haike
Prodigy 130 points

HI，

I want to initialize the DDR3 using the DDR Boot Table with SPI  NOR BOOT mode. The DDR3 uses MT41K256M16HA-125IT:E ,so,I know I need to calculate the DDR registers using  "DDR3 Register Calculate v4.xlsx”,then,I change some parameters found on the  “4Gb_DDR3L.pdf-Rev.O04/16EN” for MT41K256M16-125 ,but it didn't work, Is there something wrong I did, hope for your help.

 

6663.DDR3 Register Calc v4 - MT41K256M16HA-125E.xlsx

4Gb_DDR3L_41k.pdf

PS:  the  DDR boot table I used to boot my  previous board with DDR3 using "MT41J256M16HA-125E" successfully :

00 00 00 70  //length
00 87 35 00  //where to load ddr table to L2
02 42 80 F5  //config select
00 00 00 00  //pll Prediv
00 00 00 1C  //pll Mul
00 00 00 02  //pll post div
63 06 2A 32  //sd ram config
00 00 00 00  //sdram config 2
00 00 14 50  //sdram fresh cntrl
11 13 78 3C //sdram timing 1
30 B4 7F E3 //sdram timing 2
55 9F 8A DF //sdram timing 3
00 00 00 00
00 00 00 00
00 00 00 00
00 01 00 00 //perform count config
00 00 00 00
00 00 00 00
00 00 00 00
70 07 32 14 //sdRamoutImpedCalcfg
00 00 00 00
00 10 01 0F //ddr phy control1
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
10 00 00 00 //ecc cntrl
00 00 00 00
00 00 00 00
00 00 03 05 //rdWrtExcThresh

  • 0
    TI__Guru**** 161600 points
    Hi,

    Apologies for the delayed response. This has been forwarded to the design team.

    Best Regards,
    Yordan
  • 0
    TI__Guru** 116020 points
    Have you tested the DDR configuration values that you computed by using it in the GEL file and initializing the device using an emulator. This should help build confidence that there are no issues with the configuration values.

    Also, Note for this device the DDR PLL initialization sequence was changed after the ROM boot code was finalized and the DDR boot table doesn`t support DDR hw leveling so we dont typically recommend using DDR boot table for this initialization but some customers have successfully used this feature to initialize DDR althtough at slower speeds and then increased the DDR speed from their application code.

    Regards,
    Rahul