Question about capturing video from VGA interface and output to AM3874 VIP0 in RGB-888 format.

Further update about my experiment based on my approach above:

 After modifying three Linux driver files, I can stream video from VGA input on HDMI output when I run saLoopBackFbdev. But color is not correct. Can anyone help to identify what’s wrong and how to fix it?

 - Yong

Attaches are my patches and output image.

Index: arch/arm/mach-omap2/ti81xx_vpss.c
===================================================================
--- arch/arm/mach-omap2/ti81xx_vpss.c	(revision 263427)
+++ arch/arm/mach-omap2/ti81xx_vpss.c	(working copy)
@@ -135,7 +135,7 @@
 			.platform_data = &tvp7002_pdata,
 		},
 		.vip_port_cfg = {
-			.ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
+			.ctrlChanSel = VPS_VIP_CTRL_CHAN_DONT_CARE,
 			.ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
 			.pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
 			.invertFidPol = 0,
@@ -158,8 +158,8 @@
 		},
 		.video_capture_mode =
 		   VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
-		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,
-		.input_data_format = FVID2_DF_YUV422P,
+		.video_if_mode = VPS_CAPT_VIDEO_IF_MODE_24BIT,
+		.input_data_format = FVID2_DF_RGB24_888,
 	},
 	{
 		.name	= TVP7002_INST1,
Index: drivers/media/video/ti81xx/ti81xxvin_main.c
===================================================================
--- drivers/media/video/ti81xx/ti81xxvin_main.c	(revision 263427)
+++ drivers/media/video/ti81xx/ti81xxvin_main.c	(working copy)
@@ -390,7 +390,7 @@
 	buf_obj->fmt.fmt.pix.sizeimage = buf_obj->fmt.fmt.pix.height *
 		buf_obj->fmt.fmt.pix.width * 2 ;
 	buf_obj->fmt.fmt.pix.bytesperline = buf_obj->fmt.fmt.pix.width * 2;
-	buf_obj->fmt.fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
+	buf_obj->fmt.fmt.pix.colorspace = V4L2_COLORSPACE_SRGB;
 
 	inst->crop.left = 0;
 	inst->crop.top = 0;
@@ -558,12 +558,12 @@
 		pixfmt->pixelformat = V4L2_PIX_FMT_YUYV;
 	}
 
-	if (V4L2_COLORSPACE_REC709 != pixfmt->colorspace) {
+	if (V4L2_COLORSPACE_SRGB != pixfmt->colorspace) {
 		if (!update) {
 			ti81xxvin_dbg(2, debug, "Invalid colorspace\n");
 			goto exit;
 		}
-		pixfmt->colorspace = V4L2_COLORSPACE_REC709;
+		pixfmt->colorspace = V4L2_COLORSPACE_SRGB;
 
 	}
 	ret = ti81xxvin_get_valid_field(inst, update, &field);
Index: drivers/media/video/tvp7002.c
===================================================================
--- drivers/media/video/tvp7002.c	(revision 263427)
+++ drivers/media/video/tvp7002.c	(working copy)
@@ -104,8 +104,8 @@
 	{ TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE },
 	{ TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE },
 	{ TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE },
-	{ TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE },
-	{ TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE },
+	{ TVP7002_IN_MUX_SEL_1, 0xaa, TVP7002_WRITE },// select VGA input
+	{ TVP7002_IN_MUX_SEL_2, 0x62, TVP7002_WRITE },// select VGA HS input
 	{ TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE },
 	{ TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE },
 	{ TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE },
@@ -347,10 +347,10 @@
 	{
 		V4L2_DV_720P60,
 		tvp7002_parms_720P60,
-		V4L2_COLORSPACE_REC709,
+		V4L2_COLORSPACE_SRGB,
 		V4L2_FIELD_NONE,
 		1,
-		0x2EE,
+		0x2EA,
 		135,
 		153
 	},
@@ -503,6 +503,7 @@
 
 	c = v4l2_get_subdevdata(sd);
 
+	v4l2_info(sd, "TVP7002 write value[0x%02x] at reg[0x%02x]\n", value, addr);
 	for (retry = 0; retry < I2C_RETRY_COUNT; retry++) {
 		error = i2c_smbus_write_byte_data(c, addr, value);
 
@@ -765,7 +766,7 @@
 		}
 
 	if (index == NUM_PRESETS) {
-		v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n",
+		v4l2_info(sd, "detection failed: lpf = %x, cpl = %x\n",
 								lpfr, cpln);
 		/* Could not detect a signal, so return the 'invalid' preset */
 		qpreset->preset = V4L2_DV_INVALID;
@@ -776,7 +777,7 @@
 	qpreset->preset = presets->preset;
 
 	/* Update lines per frame and clocks per line info */
-	v4l2_dbg(1, debug, sd, "detected preset: %d\n", presets->preset);
+	v4l2_info(sd, "detected preset: %d\n", presets->preset);
 	return 0;
 }
 

hi Zou,

Can you take the dump of 10 registers from 0x48105500 and share it? It looks like some port configuration iswrong.

Rgds,

Brijesh

Hi Brijesh,

Thanks a lot for the help. Here are values of those registers:

                        Phy Addr : 0x48105500 Data : 0x00000000
                        Phy Addr : 0x48105501 Data : 0x05000000
                        Phy Addr : 0x48105502 Data : 0xa1050000
                        Phy Addr : 0x48105503 Data : 0x00a10500
                        Phy Addr : 0x48105504 Data : 0x8000a105
                        Phy Addr : 0x48105505 Data : 0x008000a1
                        Phy Addr : 0x48105506 Data : 0x00008000
                        Phy Addr : 0x48105507 Data : 0x00000080
                        Phy Addr : 0x48105508 Data : 0x00000000
                        Phy Addr : 0x48105509 Data : 0x00000000

Regards,

Yong

Hi Yong,

From the register settings, it looks like VIP is configured for embedded sync input ( Phy Addr : 0x48105504 Data : 0x8000a105), VGA input is typically discrete sync input, could you please set to for discrete sync 24bit RGB input mode? Please set the polarity of the hsync and vsync signals correctly in the VIP ports.

Can you also dump the frame into a file and see which color components are swapped? Also please make sure that RGB signals are correctly connected to corresponding RGB input of the VIP.

Regards,

Brijesh Jadav

Hi Brijesh,

Thanks a lot for the continuous support. After changing to VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC, the color of video is still not correct, but is different from previous video color.

I verified that my VGA output is OK by connecting a monitor. I assume that hardware on DM814x EVM board should be no problem. Here is register dump:

                        Phy Addr : 0x48105500 Data : 0x00000000
                        Phy Addr : 0x48105501 Data : 0x0a000000
                        Phy Addr : 0x48105502 Data : 0x200a0000
                        Phy Addr : 0x48105503 Data : 0x40200a00
                        Phy Addr : 0x48105504 Data : 0x8040200a
                        Phy Addr : 0x48105505 Data : 0x00804020
                        Phy Addr : 0x48105506 Data : 0x00008040
                        Phy Addr : 0x48105507 Data : 0x00000080
                        Phy Addr : 0x48105508 Data : 0x00000000
                        Phy Addr : 0x48105509 Data : 0x00000000

Frame-dump is attached below.

0027.captdump.rgb24.dat

Regards,

Yong

Hi Yong,

From the register dump, you are setting hsync and vsync polarity to active low, could you please check if it is correct?

Which daughter card you are using for testing VGA input? Is it catalog card?

Regards,

Brijesh Jadav

Hi Brijesh,

I am using Expansion I/O BOARD-REVD daughter card. TVP7002 in the card is used to control VGA input and decode. I found vsync output and hsync output setting in TVP7002 are active high and output format is 4:2:2 embedded sync enabled.

So I change code to set TVP7002 hsync output and vsync output as active low, also set out format is 4:4:4 30-bits and disable embedded sync. But color of video is still not correct and picture has shift. I am not sure if TVP7002 configuration is correct, here is register dump for TVP7002:

[   10.440000] tvp7002 3-005d: TVP7002 write reg[0x01] with value[0x67]
[   10.460000] tvp7002 3-005d: TVP7002 write reg[0x02] with value[0x20]
[   10.470000] tvp7002 3-005d: TVP7002 write reg[0x03] with value[0xa0]
[   10.480000] tvp7002 3-005d: TVP7002 write reg[0x04] with value[0x80]
[   10.490000] tvp7002 3-005d: TVP7002 write reg[0x05] with value[0x32]
[   10.510000] tvp7002 3-005d: TVP7002 write reg[0x06] with value[0x20]
[   10.520000] tvp7002 3-005d: TVP7002 write reg[0x07] with value[0x60]
[   10.530000] tvp7002 3-005d: TVP7002 write reg[0x08] with value[0x00]
[   10.550000] tvp7002 3-005d: TVP7002 write reg[0x09] with value[0x00]
[   10.560000] tvp7002 3-005d: TVP7002 write reg[0x0a] with value[0x00]
[   10.570000] tvp7002 3-005d: TVP7002 write reg[0x0b] with value[0x80]
[   10.590000] tvp7002 3-005d: TVP7002 write reg[0x0c] with value[0x80]
[   10.600000] tvp7002 3-005d: TVP7002 write reg[0x0d] with value[0x80]
[   10.610000] tvp7002 3-005d: TVP7002 write reg[0x0e] with value[0x20]
[   10.630000] tvp7002 3-005d: TVP7002 write reg[0x0f] with value[0x2e]
[   10.640000] tvp7002 3-005d: TVP7002 write reg[0x10] with value[0x5d]
[   10.650000] tvp7002 3-005d: TVP7002 write reg[0x11] with value[0x47]
[   10.660000] tvp7002 3-005d: TVP7002 write reg[0x12] with value[0x00]
[   10.680000] tvp7002 3-005d: TVP7002 write reg[0x13] with value[0x00]
[   10.690000] tvp7002 3-005d: TVP7002 write reg[0x15] with value[0x00]
[   10.700000] tvp7002 3-005d: TVP7002 write reg[0x16] with value[0x01]
[   10.720000] tvp7002 3-005d: TVP7002 write reg[0x17] with value[0x00]
[   10.730000] tvp7002 3-005d: TVP7002 write reg[0x18] with value[0x01]
[   10.740000] tvp7002 3-005d: TVP7002 write reg[0x19] with value[0xaa]
[   10.760000] tvp7002 3-005d: TVP7002 write reg[0x1a] with value[0x62]
[   10.770000] tvp7002 3-005d: TVP7002 write reg[0x1b] with value[0x77]
[   10.780000] tvp7002 3-005d: TVP7002 write reg[0x1c] with value[0x07]
[   10.800000] tvp7002 3-005d: TVP7002 write reg[0x1d] with value[0x00]
[   10.810000] tvp7002 3-005d: TVP7002 write reg[0x1e] with value[0x10]
[   10.820000] tvp7002 3-005d: TVP7002 write reg[0x1f] with value[0x10]
[   10.830000] tvp7002 3-005d: TVP7002 write reg[0x20] with value[0x10]
[   10.850000] tvp7002 3-005d: TVP7002 write reg[0x21] with value[0x08]
[   10.860000] tvp7002 3-005d: TVP7002 write reg[0x22] with value[0x00]
[   10.870000] tvp7002 3-005d: TVP7002 write reg[0x26] with value[0x80]
[   10.890000] tvp7002 3-005d: TVP7002 write reg[0x28] with value[0x53]
[   10.900000] tvp7002 3-005d: TVP7002 write reg[0x2a] with value[0x07]
[   10.910000] tvp7002 3-005d: TVP7002 write reg[0x2c] with value[0x50]
[   10.930000] tvp7002 3-005d: TVP7002 write reg[0x2d] with value[0x00]
[   10.940000] tvp7002 3-005d: TVP7002 write reg[0x2e] with value[0x80]
[   10.950000] tvp7002 3-005d: TVP7002 write reg[0x2f] with value[0x00]
[   10.970000] tvp7002 3-005d: TVP7002 write reg[0x30] with value[0x04]
[   10.980000] tvp7002 3-005d: TVP7002 write reg[0x31] with value[0x5a]
[   10.990000] tvp7002 3-005d: TVP7002 write reg[0x35] with value[0x10]
[   11.000000] tvp7002 3-005d: TVP7002 write reg[0x36] with value[0x00]
[   11.020000] tvp7002 3-005d: TVP7002 write reg[0x3d] with value[0x03]
[   11.030000] tvp7002 3-005d: TVP7002 write reg[0x3f] with value[0x01]
[   11.040000] tvp7002 3-005d: TVP7002 write reg[0x40] with value[0x01]
[   11.060000] tvp7002 3-005d: TVP7002 write reg[0x41] with value[0x2c]
[   11.070000] tvp7002 3-005d: TVP7002 write reg[0x42] with value[0x06]
[   11.080000] tvp7002 3-005d: TVP7002 write reg[0x43] with value[0x2c]
[   11.100000] tvp7002 3-005d: TVP7002 write reg[0x44] with value[0x05]
[   11.110000] tvp7002 3-005d: TVP7002 write reg[0x45] with value[0x00]
[   11.120000] tvp7002 3-005d: TVP7002 write reg[0x46] with value[0x1e]
[   11.140000] tvp7002 3-005d: TVP7002 write reg[0x47] with value[0x00]
[   11.150000] tvp7002 3-005d: TVP7002 write reg[0x48] with value[0x00]
[   11.160000] tvp7002 3-005d: TVP7002 write reg[0x49] with value[0x00]
[   11.170000] tvp7002 3-005d: TVP7002 write reg[0x4a] with value[0xe3]
[   11.190000] tvp7002 3-005d: TVP7002 write reg[0x4b] with value[0x16]
[   11.200000] tvp7002 3-005d: TVP7002 write reg[0x4c] with value[0x4f]
[   11.210000] tvp7002 3-005d: TVP7002 write reg[0x4d] with value[0x02]
[   11.230000] tvp7002 3-005d: TVP7002 write reg[0x4e] with value[0xce]
[   11.240000] tvp7002 3-005d: TVP7002 write reg[0x4f] with value[0x06]
[   11.250000] tvp7002 3-005d: TVP7002 write reg[0x50] with value[0xab]
[   11.270000] tvp7002 3-005d: TVP7002 write reg[0x51] with value[0xf3]
[   11.280000] tvp7002 3-005d: TVP7002 write reg[0x52] with value[0x00]
[   11.290000] tvp7002 3-005d: TVP7002 write reg[0x53] with value[0x10]
[   11.300000] tvp7002 3-005d: TVP7002 write reg[0x54] with value[0x55]
[   11.320000] tvp7002 3-005d: TVP7002 write reg[0x55] with value[0xfc]
[   11.330000] tvp7002 3-005d: TVP7002 write reg[0x56] with value[0x78]
[   11.340000] tvp7002 3-005d: TVP7002 write reg[0x57] with value[0xf1]
[   11.360000] tvp7002 3-005d: TVP7002 write reg[0x58] with value[0x88]
[   11.370000] tvp7002 3-005d: TVP7002 write reg[0x59] with value[0xfe]
[   11.380000] tvp7002 3-005d: TVP7002 write reg[0x5a] with value[0x00]
[   11.400000] tvp7002 3-005d: TVP7002 write reg[0x5b] with value[0x10]
[   11.410000] tvp7002 3-005d: TVP7002 write reg[0x0e] with value[0x00]
[   11.420000] tvp7002 3-005d: TVP7002 write reg[0x18] with value[0x00]
[   11.440000] tvp7002 3-005d: TVP7002 write reg[0x01] with value[0x67]
[   11.450000] tvp7002 3-005d: TVP7002 write reg[0x02] with value[0x20]
[   11.460000] tvp7002 3-005d: TVP7002 write reg[0x03] with value[0xa0]
[   11.470000] tvp7002 3-005d: TVP7002 write reg[0x04] with value[0x16]
[   11.490000] tvp7002 3-005d: TVP7002 write reg[0x40] with value[0x47]
[   11.500000] tvp7002 3-005d: TVP7002 write reg[0x41] with value[0x01]
[   11.510000] tvp7002 3-005d: TVP7002 write reg[0x42] with value[0x4b]
[   11.530000] tvp7002 3-005d: TVP7002 write reg[0x43] with value[0x06]
[   11.540000] tvp7002 3-005d: TVP7002 write reg[0x44] with value[0x05]
[   11.550000] tvp7002 3-005d: TVP7002 write reg[0x45] with value[0x00]
[   11.570000] tvp7002 3-005d: TVP7002 write reg[0x46] with value[0x1e]
[   11.580000] tvp7002 3-005d: TVP7002 write reg[0x47] with value[0x00]
[   11.590000] tvp7002 3-005d: TVP7002 write reg[0x31] with value[0x5a]
[   11.610000] tvp7002 3-005d: TVP7002 write reg[0x05] with value[0x32]
[   11.620000] tvp7002 3-005d: TVP7002 write reg[0x06] with value[0x20]
[   11.630000] tvp7002 3-005d: TVP7002 write reg[0x12] with value[0x00]
[   11.640000] tvp7002 3-005d: TVP7002 write reg[0x13] with value[0x00]

Note: register [0x0e (Sync Control 1)] value[0x00]: setting hsync and vsync output active low.

Attach is another frame dump and image.

6840.captdump.rgb24.dat

Regards,

Yong

Hi Yong,

Can you set the output format to RGB?

Regards,

Brijesh

Hi Brijesh,

I am not sure if my setup for output format to RGB888 is correct. I checked TVP7002 datasheet, it doesn't state clearly on how to set RGB format output. Here is my understanding about my setting on TVP7002:

1) Since VGA interface provide RGB format line signals, so TVP7002 ADC(Analog to Digital Conversion) module will get 10-bit RGB value for each line.

2) Setting by-pass CSC(color space conversion), so that RGB value will not be converted to YCrCb color space.

    reg-(MISC Control 3) [0x18] -- CSC-En bit is set as 0 (CSC disabled).

3) Setting 30-bit 4:4:4 output format and disable embedded sync.

Regards,

Yong

    reg-(Output Formatter) [0x15] -- value 0x00.

Hi Yong,

Ok let's use this TVP configuration and set the VIP input format to discrete sync RGB and output format to RGB, so there will not be any processing done inside VIP. It will dump what it gets from the TVP. In this case, can you check if you are getting correct output? 

If it is not correct, TVP settings is wrong

Regards,

Brijesh Jadav

Hi Brijesh,

The test result based on the TVP7002 setting above was already posted in May 30 and register values of VIP1 were posted in May 29. Can you check if register value of VIP1 are correct?

Regards,

Yong

Hi Yong,

There are two issues that you are seeing, one is shift in the output and second is colors are not correct.

The first issue is because of the hsync style of the capture, in this style of capture, VIP captures complete line including blanking line, so in the application, we need to crop the blanking pixels. The number of blanking pixels depends on the input standard/resolution. There is also trimmer in the VIP module, so we could trim blanking pixels in the VIP itself.

Regarding the second issue, I think, we should first dump the frame from the capture and check if it is correct. If colors are swapped, we could rearrange them using CSC, but first we need to know colors are swapped.

Also we need to check if TVP settings are correct. I will check this settings and see if it is correct.

Rgds.

brijesh

Hi Yong,

As I said, there are two issues, one is shift in the output and the second is color not correct.

First issue is because of the hsync/vsync mode of capture, In this mode, VIP captures, horizontal blanking area as well, so we have to crop those blanking pixels in the application. I am not familiar with ezSDK, so will not be able to help much here.

For the second issue, could you try out the below TVP7002 settings?

{

   0x67u,              /* HPLL_DIVIDER_MSB         */

    0x20u,              /* HPLL_DIVIDER_LSB         */

    0xA0u,              /* HPLL_CTRL                */

    0xB0u,              /* HPLL_PHASE_SELECT        */

    0x32u,              /* CLAMP_START              */

    0x20u,              /* CLAMP_WIDTH              */

    0x20u,              /* HSYNC_OUT_WIDTH          */

    0x5Bu,              /* SYNC_CTRL1               */

    0x01u,              /* HPLL_PRE_COAST           */

    0x00u,              /* HPLL_POST_COAST          */

    0x00u,              /* MISC_CTRL3               */

    0x00u,              /* IN_MUX_SELECT1           */

    0x6Au,              /* IN_MUX_SELECT2           */

    0x08u,              /* HSOUT_OUT_START          */

    0x00u,              /* MISC_CTRL4               */

    0x50u,              /* ADC_SETUP                */

    0x5Au,              /* ALC_PLACEMENT            */

    0x35u,              /* AVID_START_PIXEL_LSB     */

    0x01u,              /* AVID_START_PIXEL_MSB     */

    0x35u,              /* AVID_STOP_PIXEL_LSB      */

    0x06u,              /* AVID_STOP_PIXEL_MSB      */

    0x05u,              /* VBLK_FLD0_START_OFFSET   */

    0x00u,              /* VBLK_FLD1_START_OFFSET   */

    0x1Eu,              /* VBLK_FLD0_DURATION       */

    0x00u,              /* VBLK_FLD1_DURATION       */

    0x00u,              /* FBIT_FLD0_START_OFFSET   */

    0x00u,              /* FBIT_FLD1_START_OFFSET   */

    0x00u,                               /* OUTPUT_FORMATTER                   */

    0x10u,                               /* MISC_CTRL2                      */

    0x00u,                               /* MISC_CTRL3                      */

};

Regards,

Brijesh Jadav

Hi Brijesh,

Sorry for late response because I hadn't chance to test your suggestion. Today I finally test your suggestion. Here is test result.

With the setting of tvp7002, there is no video signal captured, I got error:

-----------------------------------

# saLoopBackFbdev
Driver Name: ti81xxvin
Driver bus info: TI81xx Platform
Driver is capable of doing capture
capt.dv_preset.preset[0]
saLoopBackFbdev:
 Mode set is 0
Setting DV Preset failed

-----------------------------------

The root cause is, setting on register IN_MUX_SELECT_1 and IN_MUX_SELECT2 selects Componet-Video-Input, but video source is VGA-INPUT.

So I change those two register settings to select VGA-INPUT only, then I can see video when I run saLoopBackFbdev, but has same issue: shifting and incorrect color.

As I know, HPVSS VIP Parser is controlled by M3 firmware, application like saLoopBackFbdev is using V4L2 API to control video capture, I need more information on how to configure HPVSS VIP Parser in Linux driver.

Regards,

Yong

Yong,

If you go to the TI product folder for the TVP7002 you will find some example command files for various input modes.

Please have a look through these setup files for one which is the same resolution and format for your application.

http://www.ti.com/product/tvp7002

(http://www.ti.com/litv/zip/slec023a)

BR,

Steve

Hi Steve,

Thanks a lot for the info.

Regards,

Yong