DS50PCI401: Layout question

Amy Chen

Part Number: DS50PCI401
Other Parts Discussed in Thread: DS160PR410

The picture below is my block diagram. I am designing a PCIe add-on card with FR4 4-layer PCB.

The entire system has 0.22uF capacitors on the CPU TX side, and the root port can support GEN3 X8 signals, while the end device on my add-on card only supports GEN2 X4 signals.
I want to use DS50PCI401 for my add-on card.
I didn't see any layout suggestions on the datasheet.
1. I want to know if there is a layout guide for DS50PCI401?
2. In my picture, do I need any capacitors on the TX or RX side of node A (between the PCIe slot and the redriver)? If capacitors are needed, what value is recommended?
3. In my picture, do I need any capacitors on the TX or RX side of node B (between the redriver and the device)? If capacitors are needed, what value is recommended?
4. At node A (between the PCIe slot and the redriver), what is the minimum and maximum limit of the trace length?
5. At node B (between the redriver and the device), what is the minimum and maximum limit of the trace length?
6. Where is the recommended location for the redriver? Near the device or the slot? Because the size of my add-on card is not very large, may the placement position be unimportant?
7. According to the data sheet, there are many hardware pins that can be set, such as EQ level, de-emphasis level, etc. I want to know if I want to set High level to 1 or Low level to 0, what is the value of the resistor PU? Or PD?
8.Are there any important layout suggestions that need attention?

Thank you very much.

over 3 years ago

0 Nasser Mohammadi over 3 years ago

TI__Guru* 92040 points

Hi Amy,

1). Please note link below for recommended schematic and board stackup information:

https://www.ti.com/lit/ug/snlu077/snlu077.pdf?ts=1622218737468&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDS50PCI401%253FkeyMatch%253DDS50PCI401%2526tisearch%253Dsearch-everything%2526usecase%253DGPN

2). In PCIe applications, normally AC coupling Cap are put on the TX side. This means we do not need AC coupling Cap on input of the DS50PCI401 - since it is already on TX side - but we do need to put AC coupling Cap on TX side of the DS50PCI401.

3). Please note #2 above.

4). Typically minimum should be about 4-5dB signal loss(please refer to table 2 of the data sheet for details). Minimum or maximum is based on the dB loss at Nyquist. Please refer to table 2 and 3 of the data sheet to realize EQ and DEM settings.

5). Please note #4.

6). At minimum we should have about 4-5dB loss and at maximum we need about 20dB loss on the input of the device.

8). You can refer to the DS160PR410 layout guidelines. Please below note link to this part's data sheet(note chapter 10 Layout):

https://www.ti.com/lit/ds/symlink/ds160pr410.pdf?ts=1622219708915&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US%2526searchTerm%253Dds160pr410%2526nr%253D125

Regards ,,, Nasser

0 Amy Chen over 3 years ago in reply to Nasser Mohammadi

Prodigy 20 points

Hi Nasser

Thank you for your reply.
But I still don’t know where is the correct location of the capacitors?
Can you draw me a simple diagram?
Or I give you the picture below is my understanding.

For the GEN2 signal, I placed 0.1uF capacitors on the TX side of the device and close to the redriver.

Is that correct?
I have one more question. I did not see the recommended PU or PD value of resistors in the data sheet. Can you suggest?

Thank you very much.

0 Nasser Mohammadi over 3 years ago in reply to Amy Chen

TI__Guru* 92040 points

Hi Amy,

1). On add-in-card rederiver TX only should have AC coupling Cap(not RX).

2). You can use a value of 1K-ohm for PD and 4.7K for PU.

Regards,, Nasser

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DS50PCI401: Layout question