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DS110DF410: make loss of lock tweaking HEO VEO threshold

user4779049
Expert 2185 points
Part Number: DS110DF410

Hi Team, 

Please advise me on a question bellow.

I am using DS1100DF410 connecting to an optical module.

During the system test, DS110DF410 report poor eye opening, when I referred address 0x27 and 0x28,

resulting excessive error on the output of the device.

It seemed to be that CTLE and DFE adaptation may not be completed in good condition.

So, in order to fix this problem, I tried to tune HEO VDO threshold from default 0x44 to 0xCC

in address 0x6a, while set bit 7 to '1' in address 0x3E (Default value is also '1')

However, DS110DF410 still show lock despite of small vale of HEO VEO in address 0x27 and 0x28.

I suspect that HEO VEO threshold may be ignored.

Q1. Can you let me know if it is true that DS110DF410 make de-assert LOCK if either VEO or HEO 

       is lower than the threshold?

Q2. Can you le me know the proper procedure wen you use HEO VDO threshold?

Q3. Can you proof above procedure using EVM?

Q4. Dose DS110DF410 refer HEO VEO only lock process, or after establish lock too?

Q5. The HEO and VEO values are 6 bits, while HEO VEO thresholds  are 4 bits.

      How  VEO/HEO and  thresholds related?

Q6. When Disable HEO/VEO lock monitoring by clearing bit 7 in address 0x3E, the auto adaptation of 

     CTEL and DFE are still effective or not?

Mita

 

  • 0
    TI__Mastermind 19185 points

    Hi Mita,

    My recommendation here would be to manually force CTLE = 0x00 (lowest boost setting.) Most likely there is signal over-equalization at the retimer input which is affecting the EQ auto adaption process. You may use the channel register write procedure below. I believe this will fix your issue. Please try it and confirm.

     

    REG

    Value

    Comment

    0x31

    0x00

    Set Adapt mode 0

    0x2D

    0x88

    Enable EQ override

    0x03

    0x00

    Set EQ = 00

    0x3A

    0x00

    Set EQ = 00

    0x0A

    0x1C

    Puts the CDR into RESET

    0x0A

    0x10

    Releases the CDR from reset

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Expert 2185 points

    Rodorig-san,

    Thank you for our advice.

    However, I want to know the answers to the questions bellow.

    Can you give me the answers to the questions bellows.

    Q1. Can you let me know if it is true that DS110DF410 make de-assert LOCK if either VEO or HEO 

           is lower than the threshold?

    Q2. Can you le me know the proper procedure wen you use HEO VDO threshold?

    Q3. Can you proof above procedure using EVM?

    Q4. Dose DS110DF410 refer HEO VEO only lock process, or after establish lock too?

    Q5. The HEO and VEO values are 6 bits, while HEO VEO thresholds  are 4 bits.

          How  VEO/HEO and  thresholds related?

    Q6. When Disable HEO/VEO lock monitoring by clearing bit 7 in address 0x3E, the auto adaptation of 

         CTEL and DFE are still effective or not?

    Mita

  • 0 in reply to user4779049
    Expert 2185 points

    Rodrigo -san,

    Can you give me any update?

    Mita

  • 0 in reply to user4779049
    TI__Mastermind 19185 points

    I will provide my feedback to your questions by close of business tomorrow, Friday USA Pacific Time.

    Thanks,

    Rodrigo Natal

    HSSC Applications Engineer

  • 0 in reply to Rodrigo Natal
    Expert 2185 points

    Rodrigo-san,

    Thank you for your feedback.

    I am looking forward to get answers.

    Mita

  • 0 in reply to user4779049
    TI__Mastermind 19185 points

    Hi Mita-san, see below.

    1. Can you let me know if it is true that DS110DF410 make de-assert LOCK if either VEO or HEO is lower than the threshold?
      • Yes, VEO and HEO values are gating parameters for CDR lock
    2. Can you le me know the proper procedure wen you use HEO VDO threshold?
      • The retimer default HEO and VEO lock thresholds are the optimal and recommended settings
    3. Q3. Can you proof above procedure using EVM?
      • The procedure of manually setting CTLE = 0x00 for the case of low input insertion loss channel has been extensively tested by TI. Furthermore it is used by multiple customers for systems currently in production
    4. Dose DS110DF410 refer HEO VEO only lock process, or after establish lock too?
      • THe retimer also has post-lock HEO and VEO thresholds, to allow it to maintain CDR lock.
    5. The HEO and VEO values are 6 bits, while HEO VEO thresholds  are 4 bits. How  VEO/HEO and  thresholds related? 
      • The calculations for these parameters are different.
      • Please refer to the datasheet register map for instructions to translate the hex value to a unit value (UI or millivolts)
    6. When Disable HEO/VEO lock monitoring by clearing bit 7 in address 0x3E, the auto adaptation of CTLE and DFE are still effective or not?
      • Correct, disabling the HEO VEO lock monitor does not disable the Rx EQ auto adaption

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Expert 2185 points

    Hi Rodrigo-san,

    Thank you for the answers.

    Please seem my in-line feedback bellows: 

    1. Can you let me know if it is true that DS110DF410 make de-assert LOCK if either VEO or HEO is lower than the threshold?
      • Yes, VEO and HEO values are gating parameters for CDR lock

    => Thank you. I understand it.

    1. Can you le me know the proper procedure wen you use HEO VDO threshold?
      • The retimer default HEO and VEO lock thresholds are the optimal and recommended settings

    => Can you change the threshold values?

    1. Q3. Can you proof above procedure using EVM?
      • The procedure of manually setting CTLE = 0x00 for the case of low input insertion loss channel has been extensively tested by TI. Furthermore it is used by multiple customers for systems currently in production

    => While maintaining adaptive CTLE and DFE mode, can you let me know how to change HEO VEO threshold?

    1. Dose DS110DF410 refer HEO VEO only lock process, or after establish lock too?
      • THe retimer also has post-lock HEO and VEO thresholds, to allow it to maintain CDR lock.

    => Are there other HEO VEO threshold register for the post-lock?

    1. The HEO and VEO values are 6 bits, while HEO VEO thresholds  are 4 bits. How  VEO/HEO and  thresholds related? 
      • The calculations for these parameters are different.
      • Please refer to the datasheet register map for instructions to translate the hex value to a unit value (UI or millivolts)

    =>Thanks. I found that threshold values needed to be multiply by 4.

    Mita

    1. When Disable HEO/VEO lock monitoring by clearing bit 7 in address 0x3E, the auto adaptation of CTLE and DFE are still effective or not?
      • Correct, disabling the HEO VEO lock monitor does not disable the Rx EQ auto adaption
  • +1 in reply to user4779049
    TI__Mastermind 19185 points

    => Can you change the threshold values? While maintaining adaptive CTLE and DFE mode, can you let me know how to change HEO VEO threshold?

    • Yes, the HEO and VEO lock thresholds can be adjusted via channel register

    Thanks,

    Rodrigo Natal

  • +1 in reply to Rodrigo Natal
    Expert 2185 points

    Rodrigo-san,

    Thank you.

    I get it.

    Mita