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DS125DF111: DS125DF111

Kevin cao
Prodigy 160 points
Part Number: DS125DF111

Hi TI technical support team，I have encountered the following problems and hope to get your help,TKS!

I have a SFP+ module project which use DS125DF111 .I use the B channel, and I am going to work at 1.25Gbps and 10.3125Gbps，but I can’t lock it in now.The following is my register configuration table

ADDRESS WRITE VALUE WRITE MASK

0xff 0x0d 0x0f

0x00 0x04 0x04

0x0a 0x0c 0x0c

0x60 0x00 0xff

0x61 0xb2 0xff

0x62 0x90 0xff

0x63 0xb3 0xff

0x64 0xcd 0xff

0x31 0x00 0x60

0x2d 0x08 0x08

0x03 0x00 0xff

0x3a 0x00 0xff

0x1e 0x08 0x08

0x2d 0x00 0x07

0x15 0x44 0x47

0x0c 0x00 0x08

0x0a 0x00 0x0c

my question is:
1. Is the lock signal related to bit3 and bit4 of register 0x02? If the signal is locked, 0x02[3&4]=1. Is my understanding correct?

2. Is the signal detected related to bit7 of register 0x54? If a signal is detected, 0x54[7]=1, right? In addition, no matter what signal it is, as long as the signal strength reaches the threshold, it can be detected, right?

3. How to use Enable Interrupt(0x56) and Interrupt Registers(0x01&0x54) correctly？I want to know status of CDR lock/CDR loss of lock/Signal Detect/Loss of Signal，How should I detect in the main program？

4.Is my above configuration correct, why can’t it be locked?

Regards,

kevin

  • 0
    TI__Expert 8585 points

    Hello Kevin,

    1. Yes, this is correct. When bits 3 and 4 of register 0x02 are 1, then the signal is locked.

    2. Correct, bit 7 of register 0x54 is the signal detect observation bit. When it is set to 1, then a signal is being detected. As long as the input signal is above 18 mVpp, the signal will be detected.

    3. In order to monitor the status of the CDR lock/loss, you must enable (set to 1) bits 3 and bit 1 of register 0x56. Once you have enabled these bits you can observe if a CDR lock interrupt has occurred in bit 1 of register 0x54 and you can observe if a CDR loss of lock has occurred in bit 4 of register 0x01. An interrupt has occurred when these bits are high (set to 1).

    In order to monitor the status of the signal detect/loss of signal, you must enable (set to 1) bits 0 and 1 of register 0x56. Once you have enabled these bits you can observe if a signal detect interrupt has occurred in bit 0 of register 0x54 and you can observe if a signal loss interrupt has occurred in bit 0 of register 0x01. An interrupt has occurred when these bits are high (set to 1).

    To sum it up, register 0x56 allows you to enable the monitoring of interrupts, but registers 0x54 bits 0 and 1 and register 0x01 bits 0 and 4 allow you to observe the status of the interrupts.

    4. To program your device for a 10.3125 Gbps data rate, please set registers 0x60 to 0x64 as shown below.

    For SFP+ host applications the PCB channel in between the retimer and the optical module can be very short. If the insertion loss of this channel is too low (less than 2dB) it can lead to CDR lock issues. For such cases, TI often recommends to manually set CTLE = 0 i.e. manually force the lowest CTLE boost setting. See recommended channel register writes procedure below.

    REG

    Value

    Comment

    0x31

    0x00

    Set Adapt mode 0

    0x2D

    0x88

    Enable EQ override

    0x03

    0x00

    Set EQ = 00

    0x3A

    0x00

    Set EQ = 00

    0x0A

    0x1C

    Puts the CDR into RESET

    0x0A

    0x10

    Releases the CDR from reset

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 160 points

    HI Kia,

    Thanks for your reply,I set register 0x56[]=0x0f,but i can not get signal detect/loss of signal interrupts and  CDR lock/loss interrupts ,i read register 0x54[]=0x80 and register 0x01[] = 0x00,but i am sure CDR is detected and  locked, as 0x02[3] =1 and 0x54[7]= 1,why?

    Another strange phenomenon is that when I use IAR to debug, the detect and lock signal indicator will light up, indicating that the signal has been detected and locked. When I power off and restart without IAR debugging, the indicator light does not light up again.I don't know why ?

  • 0 in reply to Kevin cao
    TI__Expert 8585 points

    Hello Kevin,

    The interrupt bits in register 0x54 and 0x01 are only set high if an interrupt has occurred. The primary registers you should observe are 0x02[3] and 0x54[7] to ensure the CDR is locked and a signal is detected.

    After you restart the device, the registers are all set to their default values and you must reprogram registers 0x60 to 0x64 (as shown in the table in my previous response). If you would like to keep the same configuration on the device after a power reset, then you must program the EEPROM of the device with the register values shown above.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 160 points

    Hello Kia,

       TKS，i get it.another question is about LOOPBACK related to Control and Shared Register 0x07,Loopback Input of Channel B to output of Channel A,My question is whether the input signal of channel B is directly output to the output port of channel A without CTLE\CDR\PRE-DE? or instead?

    Regards,

    kevin

  • 0 in reply to Kevin cao
    Prodigy 160 points

    Hello Kia,

       I set 0x07[1] = 1,The current has increased than before, but it doesn’t seem to work。

    Regarding the loopback, how should I set it up? I want loopback Input of Channel B to output of Channel A.

    Regards,

    kevin

  • +1 in reply to Kevin cao
    TI__Expert 8585 points

    Hello Kevin,

    As shown in the image below, the loopback input of channel B will have CDR and CTLE processing prior to being looped back. After the input signal is looped back it will have PRE-DE.

    To setup loopback, you must set 0x07[1] to 1. The issue you might be facing is that your CTLE is too high.

    Please manually force CTLE = 0x00. This can be done using the register sequence below.

    Step Register Address Register Value Write Mask Description
    1 0x0A 0x0C 0x0C Assert CDR Reset
    2 0x2D 0x08 0x08 Override CTLE Setting
    3 0x03 0x00 0xFF Set CTLE to 0x00
    4 0x0A 0x00 0x0C Release CDR Reset

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 160 points

    Hello Kia,

    I get it ,TKS!

    Regards,

    kevin