DS90UB948-Q1: Circuit Review for [Fisker Inc./Foxconn]

YT Tso

Intellectual 1770 points

Part Number: DS90UB948-Q1

Hello,

Please see attach file for Fisker/Foxconn circuit review

Thanks

CLUSTER_P0_SCHEMATIC_20210603.pdf

over 3 years ago

+1 Zoe Nuyens over 3 years ago

TI__Expert 3055 points

Hello YT,

Please see feedback attached.

CLUSTER_P0_SCHEMATIC_20210603_fbk.pdf

0 YT Tso over 3 years ago in reply to Zoe Nuyens

TI__Intellectual 1770 points

Hi Zoe,

Thanks your help ^^

0 YT Tso over 3 years ago in reply to Zoe Nuyens

TI__Intellectual 1770 points

Hi Zoe, Foxconn ask will 1280x52 resolution is too low for 924? Since CLK rate only 4MHz if frame rate use 60Hz

+1 Casey McCrea over 3 years ago in reply to YT Tso

TI__Guru** 103215 points

Hello YT,

924 has a minimum PCLK rate of 5MHz. Please make sure to include blanking into your calculation for frame rate here as 4MHz sounds like it is calculated only using the active dimensions of the video. But is your question about 924 or 948? Because the schematic above looks like it is for 948.

Best Regards,

Casey

0 YT Tso over 3 years ago in reply to Casey McCrea

TI__Intellectual 1770 points

Hi Casey, Got it! I will double check with Foxconn, thanks YT

0 YT Tso over 3 years ago in reply to Casey McCrea

TI__Intellectual 1770 points

Hi Casey,

0 YT Tso over 3 years ago in reply to Casey McCrea

TI__Intellectual 1770 points

Hi Casey, Foxconn ask 1. if our setting "LSB" means JEDIA format, and "MSB" means VESA format? Dose our understand is correct? 2. For the video setting shall we follow source side video format? Thanks! YT

+1 Casey McCrea over 3 years ago in reply to YT Tso

TI__Guru** 103215 points

Hello YT,

Here is a table to help decode the MAPSEL settings:

	24 Bit Mode	18 Bit Mode
MAPSEL = H	OLDI/SPWG/VESA	4 Lane 18 Bit Mode
MAPSEL = L	JEIDA	Standard 18 bit

Best Regards,

Casey

0 YT Tso over 3 years ago in reply to Casey McCrea

TI__Intellectual 1770 points

Thanks Casey! ^^

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DS90UB948-Q1: Circuit Review for [Fisker Inc./Foxconn]