DP83867IR: 1000BASE-T Autonegotiation Data transmission / reception

Hello yoshihito takahashi

Thank you for the Query.

Can you please provide some additional details on how the data is being sent and received.

Can you check if all the basic hardware diagnostics tests on the board works.

Do you have a schematics for review.

Regards,

Sreenivasa

Hello Sreenivasa san

> Can you please provide some additional details on how the data is being sent and received.

Can you check if all the basic hardware diagnostics tests on the board works.

⇒ Linked up with 1000BASE-T, RGMII. Below are the register settings.

Basic Mode Control Register (BMCR), Address 0x0000

reg0_set(15) <= '0'; --RESET
reg0_set(14) <= '0'; --LOOPBACK
reg0_set(13) <= '0'; --SPEED SELECTION LSB
reg0_set(12) <= '1'; --AUTO-NEGOTIATION ENABLE
reg0_set(11) <= '0'; --POWER DOWN
reg0_set(10) <= '0'; --ISOLATE
reg0_set( 9) <= '0'; --RESTART AUTO-NEGOTIATION
reg0_set( 8) <= '1'; --DUPLEX MODE
reg0_set( 7) <= '0'; --COLLISION TEST
reg0_set( 6) <= '1'; --SPEED SELECTION MSB
reg0_set( 5) <= '0'; --↓RESERVED
reg0_set( 4) <= '0';
reg0_set( 3) <= '0';
reg0_set( 2) <= '0';
reg0_set( 1) <= '0';
reg0_set( 0) <= '0';

Auto-Negotiation Advertisement Register (ANAR), Address 0x0004

reg4_set(15) <= '0'; --NP
reg4_set(14) <= '0'; --RESERVED
reg4_set(13) <= '0'; --RF
reg4_set(12) <= '0'; --RESERVED
reg4_set(11) <= '0'; --ASM_DIR
reg4_set(10) <= '0'; --PAUSE
reg4_set( 9) <= '0'; --T4
reg4_set( 8) <= '0'; --TX_FD
reg4_set( 7) <= '0'; --TX
reg4_set( 6) <= '0'; --10_FD
reg4_set( 5) <= '0'; --10BASETe_EN
reg4_set( 4) <= '0'; --↓SELECTOR
reg4_set( 3) <= '0';
reg4_set( 2) <= '0';
reg4_set( 1) <= '0';
reg4_set( 0) <= '1';

Configuration Register 1 (CFG1), Address 0x0009

reg9_set(15) <= '0'; --↓TEST MODE
reg9_set(14) <= '0';
reg9_set(13) <= '0';
reg9_set(12) <= '0'; --MASTER / SLAVE MANUAL CONFIGURATION
reg9_set(11) <= '0'; --MASTER / SLAVE CONFIGURATION VALUE
reg9_set(10) <= '0'; --PORT TYPE
reg9_set( 9) <= '1'; --1000BASE-T FULL DUPLEX
reg9_set( 8) <= '0'; --1000BASE-T HALF DUPLEX
reg9_set( 7) <= '0'; --TDR AUTO RUN
reg9_set( 6) <= '0'; --↓RESERVED
reg9_set( 5) <= '0';
reg9_set( 4) <= '0';
reg9_set( 3) <= '0';
reg9_set( 2) <= '0';
reg9_set( 1) <= '0';
reg9_set( 0) <= '0';

Register Control Register (REGCR), Address 0x000D

reg13_0_set(15) <= '0'; --↓Function
reg13_0_set(14) <= '0';
reg13_0_set(13) <= '0'; --↓RESERVED
reg13_0_set(12) <= '0';
reg13_0_set(11) <= '0';
reg13_0_set(10) <= '0';
reg13_0_set( 9) <= '0';
reg13_0_set( 8) <= '0';
reg13_0_set( 7) <= '0';
reg13_0_set( 6) <= '0';
reg13_0_set( 5) <= '0';
reg13_0_set( 4) <= '1'; --↓DEVAD
reg13_0_set( 3) <= '1';
reg13_0_set( 2) <= '1';
reg13_0_set( 1) <= '1';
reg13_0_set( 0) <= '1';

Address or Data Register (ADDAR) address 0x000E

reg14_0_set(15) <= '0'; --↓Address / Data
reg14_0_set(14) <= '0';
reg14_0_set(13) <= '0';
reg14_0_set(12) <= '0';
reg14_0_set(11) <= '0';
reg14_0_set(10) <= '0';
reg14_0_set( 9) <= '0';
reg14_0_set( 8) <= '0';
reg14_0_set( 7) <= '0';
reg14_0_set( 6) <= '0';
reg14_0_set( 5) <= '1';
reg14_0_set( 4) <= '1';
reg14_0_set( 3) <= '0';
reg14_0_set( 2) <= '0';
reg14_0_set( 1) <= '1';
reg14_0_set( 0) <= '0';

Register Control Register (REGCR), Address 0x000D

reg13_1_set(15) <= '1'; --↓Function
reg13_1_set(14) <= '0';
reg13_1_set(13) <= '0'; --↓RESERVED
reg13_1_set(12) <= '0';
reg13_1_set(11) <= '0';
reg13_1_set(10) <= '0';
reg13_1_set( 9) <= '0';
reg13_1_set( 8) <= '0';
reg13_1_set( 7) <= '0';
reg13_1_set( 6) <= '0';
reg13_1_set( 5) <= '0';
reg13_1_set( 4) <= '1'; --↓DEVAD
reg13_1_set( 3) <= '1';
reg13_1_set( 2) <= '1';
reg13_1_set( 1) <= '1';
reg13_1_set( 0) <= '1';

Address or Data Register (ADDAR) address 0x000E

reg14_1_set(15) <= '0'; --↓Address / Data ↓RESERVED
reg14_1_set(14) <= '0';
reg14_1_set(13) <= '0';
reg14_1_set(12) <= '0';
reg14_1_set(11) <= '0';
reg14_1_set(10) <= '0';
reg14_1_set( 9) <= '0';
reg14_1_set( 8) <= '0';
reg14_1_set( 7) <= '1'; -- RGMII_EN
reg14_1_set( 6) <= '1'; -- ↓RGMII_RX_HALF_FULL_THR
reg14_1_set( 5) <= '0';
reg14_1_set( 4) <= '1'; -- ↓RGMII_TX_HALF_FULL_THR
reg14_1_set( 3) <= '0';
reg14_1_set( 2) <= '0'; -- RESERVED
reg14_1_set( 1) <= '0'; -- RGMII_TX_CLK_DELAY
reg14_1_set( 0) <= '0'; -- RGMII_RX_CLK_DELAY

PHY Control Register (PHYCR), Address 0x0010

reg16_set(15) <= '0'; -- TX FIFO Depth
reg16_set(14) <= '0'; -- TX FIFO Depth
reg16_set(13) <= '0'; -- ↓RESERVED
reg16_set(12) <= '0';
reg16_set(11) <= '0';
reg16_set(10) <= '0'; -- FORCE_LINK_GOOD
reg16_set( 9) <= '0'; -- POWER_SAVE_MODE
reg16_set( 8) <= '0'; -- POWER_SAVE_MODE
reg16_set( 7) <= '0'; -- DEEP_POWER_DOWN_EN
reg16_set( 6) <= '1'; -- MDI_CROSSOVER
reg16_set( 5) <= '0'; -- MDI_CROSSOVER
reg16_set( 4) <= '0'; -- DISABLE_CLK_125
reg16_set( 3) <= '0'; -- RESERVED
reg16_set( 2) <= '0'; -- STANDBY_MODE
reg16_set( 1) <= '0'; -- LINE_DRIVER_INV_EN
reg16_set( 0) <= '0'; -- DISABLE_JABBER

The hardware uses the Xilinx sp701 evaluation board.

Two DP83867IRs are installed.

Each DP83867IR is wired to the FPGA. In FPGA, DP83867IR

DP83867IR①　　　 DP83867IR②
・rxd　　　 　 →　 txd　　
・rx_clk　 　　→　 gtx_clk
・rx_dv_rx_ctrl →　 tx_en_tx_ctrl
・txd　　　      ←　 rxd　　
・gtx_clk　       ←　 rx_clk
・tx_en_tx_ctrl ←　 rx_dv_rx_ctrl

Connect and Using a PC,

DP83867IR ①⇔DP83867IR②

I am trying to confirm communication between them.

・ Send ping

・ Throughput confirmation using [ iperf2 ]

But both are errors.

The above register setting to DP83867IR is controlled by MDIO from FPGA.

It is done every DP83867IR.

> Do you have a schematics for review.

⇒
About the circuit connection of DP83867IR, the circuit diagram of the attached evaluation board See pages 8-10.

It has been confirmed that rx_clk changes to 25MHz at 100BASE-T and 125MHz at 1000BASE-T, and rx_dv_rx_ctrl is also output after linking up.
Only rx_d is fixed at "1101".

・INT_PDWN is fixed to "H" and the IC is enabled.
・ RESET_B is usually "H" , reset "L" .
・ Of course, the external clock 25MHz is also input.

Since I am using the evaluation board I purchased,
The cause is the register setting of DP83867IR or
Assume there is a problem with the signal connection between the DP83867IRs.

I have to solve this problem urgently.
We look forward to your advice.

Regards,

takahashi

 0381874r01.pdf

Hello takahashi

Thank you for the inputs.

Couple of points 

RGMII delay 

Can you check what is the delay the xilinx reference board used and confirm if you are using the same delay. 

Please refer to below for additional information on RGMII delay adustment

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/563614/dp83867ir-dp83867-rgmii-clock-delay

https://www.ti.com/lit/pdf/snla243#:~:text=NOTE%3A%20DP83867%20allows%20adjustment%20of,by%200.25%20to%20be%20valid.&text=Using%20Equation%201%20through%20Equation,selected%20ID%20and%20PCB%20skew.

Can you also check if customer has provision to do the MII loopback and digital loopback tests.

Regards,

Sreenivasa

Hello Sreenivasa san

Sincerest apologies.
Due to my mistake, the data from RX_D [0 ... 3] of DP83867IR
It was captured in the FPGA.

But,
When I checked the loopback under the connection conditions I contacted earlier, An error will occur.

> Can you check what is the delay the xilinx reference board used and confirm if you are using the same delay.

⇒ yes. I will Confirm.

> Can you also check if customer has provision to do the MII loopback and digital loopback tests.

⇒ I'm sorry. I didn't understand much.
Does it mean to reconfirm the environment for confirming loopback?

Regards,

takahashi

Hello takahashi

Thank you for the inputs. 

Due to my mistake, the data from RX_D [0 ... 3] of DP83867IR
It was captured in the FPGA.

Could you please explain what you meant here.

I waned to ask customer to perform loopback tests like MII loopback and digital loopback.

Regards,

Sreenivasa

Hello Sreenivasa san

I told that only "1101" is output from RX_D [0 ... 3] of　DP83867IR,

data including preamble and SFD is output.Was being done.

Since I was able to confirm the above, I think that there is no problem with the delay of RGMII, but is the recognition correct?

Regards,

takahashi

Hello takahashi

Noted.

I am not sure if the preamble and the SFD would confirm that functioning of the RGMII interface ( 2 way).

I would help to optimize the delay if customer does a loop back test with the delay setting specified for xilinx board.

Regards,

Sreenivasa

Hello Sreenivasa san

We will contact you again.

We haven't solved this problem yet.

You have asked me to confirm the following two points regarding this issue.

(1) Loopback method
(2) RGMII delay

There is no problem with (1).

Let me ask you a question about (2).

Looking at the circuit diagram I sent the other day, I recognize that the delay cannot be set by the hardware strap because DP83867IR PAP is installed.

In other words, the RGMII delay of this sp701 evaluation board is
The following registers must be set using MDIO from FPGA.
Register 0x0032
Register 0x0086

Is this perception correct?

Regards,

takahashi

Hello Sreenivasa san

What does the following mean?

> Based on the inputs, can i assume that customer has done the SGMII tests have been done and works.

MII loopback test
Register '0'

Digital loopback test
Register '16'

Did you use the above, send the reference data from the MAC side, compare it with the loopback data, and confirm that there is no problem? Does that mean?

> My suggestion is to use the delay values ​​that xilinx along with the board to start with.

⇒ Unfortunately, I have not been able to confirm it.
For the time being, I will try various delay settings,
Can you think of other factors regarding this issue?

Regards,

takahashi

Hello takahashi-san, 

The following registers are used 

Loop back

0X0000, 0X0016, 0X00FE

For the delay control, if you don not have a default value, please refer to the below as a guide

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/563614/dp83867ir-dp83867-rgmii-clock-delay

http://www.ti.com/lit/an/snla243/snla243.pdf

I will let you know if there are any further inputs.

Regards,

Sreenivasa

Hello Sreenivasa san

0X00FE

What is this register used for?

――――――――――――――――――――

0X0000, 0X0016

It seems that loopback confirmation can be performed only by setting the above two registers.

Regards,

takahashi

Hello takahashi-san, 

Please refer to the datasheet and this is a recommendation.

8.4.4.1 Near-End Loopback

When configuring loopback modes, the Loopback Configuration Register (LOOPCR), address 0x00FE, should be set to 0xE720.

Regards,

Sreenivasa

Hello Sreenivasa san

Thank you for your reply.

This issue has been resolved.

After all, it was due to the delay of RGMII.

I was able to find a delay setting to clear the ping.

Thank you for your kind advice.

I would like to confirm one more point.

In the case of 1000BASE-T, from PHY to MAC, 125MHz CLK
I think that 4-bit data will come at the rising and falling edges.
The beginning of the data (first preamble) is always CLK
Does it start from the start?
Is there a case where the data starts from the falling edge of CLK?

Please confirm.

Regards,

takahashi

Hello Sreenivasa san

Excuse me.
I don't understand the meaning of the message below.
-------------------------------------------------- --------------------------------------------------
> Any idea what was the setting --2 ns
-------------------------------------------------- --------------------------------------------------

> Since the clock is 125 M, that data needs to e transferred on rising and falling edge.

I dont see an option to change the clock phase based on the datasheet.

I will do a check with the team.

⇒ According to
　Data sheet P 33 [8.4.1.1.1 1000-Mbps Mode Operation]

125MHz DDR 8bit,
At the rising edge of CLK [3_0],
At the falling edge of CLK [7_4]
It is a transfer.
In other words, 8-bit (1Byte) data is always on the rising edge.
We recognize that we will start sending and receiving.
Correct?

Regards,

takahashi

Hello takahashi-san, 

Not sure if my question was clear.

I wanted to check what was the RGMII delay that was programmed by the customer to make the interface work.

Regarding the data transfer your understanding is correct.

Regards,

Sreenivasa

Hello Sreenivasa san

I'm sorry to contact you often.

I would like to confirm the following additionally.

PHY ⇒ MAC RX_CLK
MAC ⇒ PHY GTX_CLK

In operation with 1000BASE-T RGMII,
Do RX_CLK and GTX_CLK need to be synchronized?

Currently, the PHY and MAC use different oscillator sources,
Although they are 125MHz, they are not synchronized.

Please confirm.

Regards,

takahashi

Hello Sreenivasa san

Thank you for the immediate reply.

understood. thank you.

Regards,

takahashi