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TL16C750E: THR interrupt is triggered, even the THR is holding data

Jason Chen2
Prodigy 50 points
Part Number: TL16C750E

The issue is depicted as title.

The following is the sequence of register setting to reproduce it.

#Enable enhanced function and Auto RTS/CTS

set 0x3 0xbf

set 0x2 0xd0

#Exit enhanced regist, Set 8N1

set 0x3 0x3

#Set 115200 8N1

set 0x3 0x83

set 0x0 0x8

set 0x1 0x0

set 0x7 0x0

set 0x3 0x03

#Enable INT pin, RTS/DTR

set 0x4 0x0b

#Init FIFO

set 0x4 0x4b

#Set TCR 32/96

set 0x6 0x4c

#Set TLR 96/0

set 0x7 0xc0

set 0x4 0x0b

set 0x2 0x06

set 0x2 0x01

#Deassert RTS from opposite serial port

#Send some data to THR

set 0x00 0x33

set 0x00 0x34

set 0x00 0x35

#Read LSR and confirm the TX is no empty

read 0x05 = 0x00

#Enable the THR interrupt in IER, I expect the interrupt should not be triggered.

set 0x01 0x02

#Interrupt service routine is served here.

  • 0
    TI__Guru 53860 points

    Hey Jason,

    Thanks for reporting this to us (as you pointed out in your email offline).

    Out of curiosity, does the IIR flag the interrupt as a THR empty flag?

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    Prodigy 50 points

    Hi Bobby,

    I think I have the misunderstanding about the TX FIFO trigger level. The number of trigger level means the number of spaces available instead of the threshold of the byte count, thus the interrupt is always triggered once I reenable the interrupt in IER. This issue has been solved for me. Thank you.