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XIO2001: XIO2001 PCB layout

Robert Liu
Prodigy 60 points
Part Number: XIO2001

Hello, my design is to expand two PCI slots with xio2001，There are the following PCB layout  questions:

1、Should the routing length of the clock signal pciclk1 connected to PCI slot 1 by xio2001 be equal to that of the clock signal pciclk2 connected to PCI slot 2 by xio2001?

2、Do the signals in PCI slot 1 that are synchronized with the clock signal pciclk1, such as the signal of ad31-0, have the same length?

3、Fbclk routing length requirements?

4、Is the clock signal pciclk of PCI slot 2.5 inches shorter than the length of ad32-0 signal?

thank you

  • 0
    TI__Guru* 91580 points

    Hi Robert,

    1). These could be different length. The main requirement is that feedback clock from CLKOUT6 should be longer than clocks to the downstream parts. This provides more settling time for the downstream devices.

    2). It is a good idea to provide the same length. This provides the same timing margin for all the signals.

    3). Feed back clock should longer than the longest clock signal by about a couple of inches.

    4). About 2.5 inches shorter than the longest CLKOUT signals. AD32-0 are driven by these clock signals.

    Regards,,Nasser 

  • 0
    Prodigy 60 points

    Thank you very much for your reply. My question is: (as shown in the figure above)

    1、Must the length L1 of pciclk1 be equal to the length L2 of pciclk2?

    2、Must the length L1 of pciclk1 be equal to the length L3 of ad32-0? What is the allowable deviation L1-L3?

    3、Must the length L2of pciclk1 be equal to the length L3+L4  of ad32-0? What is the allowable deviation L2-(L3+L4)?

    4、Fbclk routing length L5 Relationship between length of L1  pciclk1 and length of L2  pciclk2?  L5 = L2+2500mil？

    thank you very much！

  • 0 in reply to Robert Liu
    TI__Guru* 91580 points

    Hi Robert,

    Thanks for clarifying and please note comments below. 

    1). Length of L1 and L2 need not to be the same.

    2). They do not need to have the same length. Please note there is setup and hold time for AD(31-0) and that needs to conform to the data sheet requirements.

    3). What is important is the setup and hold time of AD lanes with respect to clocks. 

    4). Yes your understanding is correct.

    Regards ,,Nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 60 points

    Thank you very much for your reply. My question：

    1、L1 = L3(max)-1000mil?

    2、L2 = (L3+L4)(max)-1000mil?

    thank you very much！

  • 0 in reply to Robert Liu
    Prodigy 60 points

    Thank you very much for your reply. My question：

    because at PCI add in card ,PCI_CLK length = 2500mil, PCI AD31..0,,,, length max = 1500mil，should be length matched PCI_CLK and PCI Signals PCI AD31..0,,,,

    1、L1 = L3(max)-1000mil?

    2、L2 = (L3+L4)(max)-1000mil?

    thank you very much！

  • +1 in reply to Robert Liu
    TI__Guru* 91580 points

    Hi Robert,

    1). Your L1 & L2 equations are fine. Please note L1 & L2 should be less than L5.

    2). Please note setup and hold time - as noted in figure 7-4 of the data sheet - should have priority and maintained.

    Regards ,,Nasser