SN65DSI83-Q1: Issue for video output with using sn65dsi83

Dipak Shetye

Part Number: SN65DSI83-Q1
Other Parts Discussed in Thread: SN65DSI83, SN65DSI84

Hi,

I'm working on IM8M Nano android10 platform for video output. Connected lcd device of OSD [OSD070T3856-81TS] LVDS display using SN65DSI83 as a bridge converter and FT5X46 is single-chip capacitive touch panel controllers with board.

Please help me to add this device into kernel and bootloader files to display video output on lcd.

I am sharing kernel and other android files with you. I tried adding a code to the device tree file associated with lvds bridge [SN65DSI83].

I added “sn65dsi83” folder intovideo_files_android_10.zip

android_build/vendor/nxp-opensource/kernel_imx/drivers/gpu/drm/bridge/

path and, also, I added sn65dsi83 folder into the Kconfig and Makefile available in this path.

I am sharing kernel and other android files with you. I tried adding a code to the dts file associated with lvds bridge [SN65DSI83].

Please check that the updated program is correct or incorrect.

over 3 years ago

0 David (ASIC) Liu over 3 years ago

TI__Guru**** 166781 points

Hi,

Unfortunately we can not review the Linux driver implementation. Have you used the DSI Tuner to generate the DSI83 register programming value?

2705.DSI Tuner 2.1.zip

Thanks

David

0 Dipak Shetye over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

HI,

Can you check the device tree file of added sn65dsi83 bridge connection program ?

0 David (ASIC) Liu over 3 years ago in reply to Dipak Shetye

TI__Guru**** 166781 points

Hi,

I see this in the .dts

dsi_lvds_bridge: sn65dsi84@2c {

compatible = "ti,sn65dsi83";

reg = <0x2c>;

ti,dsi-lanes = <4>;

ti,lvds-format = <1>;

ti,lvds-bpp = <24>;

ti,width-mm = <217>;

ti,height-mm = <136>;

enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;

interrupt-parent = <&gpio3>;

interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_lvds>;

status = "okay";

display-timings {

lvds0_hsd101pfw2: timing@1 {

clock-frequency = <45000000>;

hactive = <1024>;

vactive = <600>;

hfront-porch = <120>;

hback-porch = <1>;

hsync-len = <8>;

vback-porch = <10>;

vfront-porch = <1>;

vsync-len = <6>;

hsync-active = <1>;

vsync-active = <1>;

de-active = <1>;

pixelclk-active = <0>;

};

port {

dsi_lvds_bridge_in: endpoint {

remote-endpoint = <&mipi_dsi_lvds_out>;

};

dsi_lvds_bridge: sn65dsi84@2c {

compatible = "ti,sn65dsi83";

reg = <0x2c>;

ti,dsi-lanes = <4>;

ti,lvds-format = <1>;

ti,lvds-bpp = <24>;

ti,width-mm = <217>;

ti,height-mm = <136>;

enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;

interrupt-parent = <&gpio3>;

interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_lvds>;

status = "okay";

display-timings {

native-mode = <&timing0>;

timing0: 1280x800_60Hz {

clock-frequency = <70360000>;

hactive = <1280>;

vactive = <800>;

hback-porch = <90>;

hfront-porch = <30>;

vback-porch = <8>;

vfront-porch = <6>;

hsync-len = <30>;

vsync-len = <6>;

hsync-active = <2>;

vsync-active = <2>;

de-active = <1>;

};

// native-mode = <&lvds0_g101evn010>;

/* AUO G101EVN01.0 */

lvds0_g101evn010: timing@0 {

clock-frequency = <69000000>;

hactive = <1280>;

vactive = <800>;

hfront-porch = <120>;

hback-porch = <1>;

hsync-len = <8>;

vback-porch = <10>;

vfront-porch = <1>;

vsync-len = <6>;

hsync-active = <1>;

vsync-active = <1>;

de-active = <1>;

pixelclk-active = <0>;

};

/* Fusion 10" F10A-0102 */

/* lvds0_hsd101pfw2: timing@1 {

clock-frequency = <45000000>;

hactive = <1024>;

vactive = <600>;

hfront-porch = <120>;

hback-porch = <1>;

hsync-len = <8>;

vback-porch = <10>;

vfront-porch = <1>;

vsync-len = <6>;

hsync-active = <1>;

vsync-active = <1>;

de-active = <1>;

pixelclk-active = <0>;

};

port {

dsi_lvds_bridge_in: endpoint {

remote-endpoint = <&mipi_dsi_lvds_out>;

};

Do you have the actual programming value of the DSI83 registers that I can check? Can you also share the panel spec?

Thanks

David

0 Dipak Shetye over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

I don't have actual programming value of the DSI83 registers. Please find attached schematic for the adapter for the display.

The driver for the LCD panel, it’s a NT71357 from Novatek.

7InchesDisplayAdapter.pdf

0 David (ASIC) Liu over 3 years ago in reply to Dipak Shetye

TI__Guru**** 166781 points

Hi,

The schematic looks ok, I would provide an option for the external ref clock if there is too much jitter on the DSI clock.

The DSI83 needs to be programmed based on the LVDS panel spec, you can use the DSI Tuner in my previous response to generate the programmed value.

Thanks

David

0 Dipak Shetye over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Hi,

Okay, Thanks for the reply.

I will be use this dsi tuner but I want to know the program or code for lvds DSI83 bridge for imx8mn. What code I will be add and where in files ?

Please send me the program lines.

0 Dipak Shetye over 3 years ago in reply to Dipak Shetye

Prodigy 10 points

Hi,

Please check in the screenshots of dsi tuner application filled with inputs value are correct for sn65dsi83 device ?

0 David (ASIC) Liu over 3 years ago in reply to Dipak Shetye

TI__Guru**** 166781 points

Hi,

The DSI clock frequency of 40MHz is too low, and you can see the DSI Tuner gives a red 'X'. You need MIN DSI Ch* CLK REQUIREMENT (MHz) of 360MHz to meet the line time on the LVDS interface.

For more info on the DSI Tuner, please refer to this link, https://www.ti.com/lit/an/slla332b/slla332b.pdf.

Thanks

David

0 Dipak Shetye over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

Hi,

Thanks for your reply.

I referred the sn65dsi83 doc to fill these panel and dsi inputs. I don't understand what input value will be filled in the clock section ?