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DS92LV0422: About PDB

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Guru 21045 points
Part Number: DS92LV0422
Other Parts Discussed in Thread: DS92LV0421

Hi Team,

 

I have two questions.

 

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[Q1]

I guess that if PDB is “0”, PLL of DS92LV0422 is reset.

Is my understanding correct?

 

<Background to a question>

I can find “the PLL is shut down” at “Pin Functions: DS92LV0421” but can’t find “the PLL is shut down” at “Pin Functions: DS92LV0422”.

So, is there a difference between " DS92LV0421" and " DS92LV0422"?

 

[Q2]

I would like to know the toggle(High -> Low -> High) timing spec of PDB.

Could you please let us know the minimum time for low period if you have any information?

 

<Image>

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Regards,

Hide

  • +1
    TI__Mastermind 24455 points

    Hi Hide,

    Q1:

    Your understanding is generally correct. I believe it is not specifically listed as "PLL is shut down" on DES because of the nature of the purpose of a PLL on the DES side. On the DES side, PLL will lose lock during PDB from either side, so I believe the result is essentially the same.

    Q2:

    We don't specifically spec the minimum low time for PDB, however there is a spec for the power down delay, which is the time it takes for the device to power down after PDB is pulled low. For the DS92LV0422, this time is tTPDD, and for the DS92LV0421, this time is tXZD:

    DS92LV0421:

    DS92LV0422:

    Regards,

    Ben

  • 0 in reply to Ben Dattilo
    Guru 21045 points

    Hi Ben-san,

    Thank you for your prompt reply.

    Regards,

    Hide