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DS110DF410: questions

Ivy Jin
Intellectual 2660 points
Part Number: DS110DF410

Hi team,

May I ask why capacitive isolation is required in the above figure? 
After the resistance 100 ohms, 2.5V is divided into 1.75V, but the high Viet threshold is also specified as 1.75V in the datasheet, if there is a safety issue with this critical voltage?
If the customer has to use a clock Daisy chain design, the REFCLK_out of A connect to B’s REFCLK_in.
Do they also need to add a capacitor similar to this, also pulling up and down two 100 ohm resistors?
Thanks!
Regards,
Ivy
  • 0
    TI__Mastermind 20192 points

    Hi Ivy,

    Capacitive isolation is used here since it is possible for a user to use their own clock source with an unknown DC offset.

    The resistive divider is used to DC bias the clock signal at 1/2 of VDD.

    If a customer is daisy chaining the DS110DF410 REFCLK_OUT to REFCLK_IN, these can be directly connected without any additional components.  Please see the excerpt from the datasheet below.

    Thanks,

    Drew