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DS90UB953-Q1: Output picture shaking

Amy Luo
Expert 6890 points
Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: ALP

Hi team,

One of our customers' questions are as follows

1. Problem background:

At present, Qualcomm platform is used to output DSI image data, and then a bridge chip is used to convert DSI to CSI signal to obtain CSI signal.

Then use DS90UB953+DS90UB960 to transmit the CSI signal to another platform through FPD-LINK for reception. The platform will preview the CSI output signal of 960 directly as camera data.

2. Current issues:

When the receiving platform previews the data, it is found that the picture is shaking, and it looks like some pixels are slightly jumping horizontally.

3. Direction checked:

Configure the bridge chip to the pattern output mode. In this case, the preview screen is still shaking.

Configure DS90UB953 to pattern output mode. In this case, the preview screen will no longer shake.

From the above experiments, we think that there may be a problem with the 953 state, resulting in shake, but we are not sure how to troubleshoot it. When the problem occurs, we dump the 953 register. The results are as follows. Please help confirm the 953 state.

Best Regards,

Amy Luo

  • 0
    TI__Guru* 83920 points

    Hello Amy,

    I will review the provided data and come back to you at the biggining of next week!

  • 0 in reply to Hamzeh Jaradat
    TI__Guru* 83920 points

    Hello Amy,

    Can you confirm that your DSI to CSI bridge is using 4 CSI lanes?

    Also can you confirm your 953 is using the Mode "Non Sync External CLK"?

    Can you provide register dump from the 960 in error case? (please in text form not as screen shot)!!

    Can you also provide schematic from your 953 and 960?

  • 0 in reply to Hamzeh Jaradat
    TI__Expert 6890 points

    Hi Hamzeh,

    Thank you for your reply. The customer's feedback on the above questions is as follows:

    1. Yes, DSI to CSI bridge is using 4 CSI lanes

    2. The 953 terminal uses the "Non Sync External CLK" mode, and the external crystal oscillator is 50MHz

    3. 960 is debugged by the client. At present, there is no way to dump all registers. The client only provides the results of the following four registers: (under abnormal conditions) 0x4c = 0x24，0x54 = 0x0，0x51 = 0x0

    4. Sorry, because the product is still in the research and development stage, it is not convenient to provide information related to schematic diagram for the time being

    More validation results:

    DSI-CSI bridge chip is configured with pattern output. The output picture will shake at 30fps and not at 60fps. For this phenomenon that the high frame rate is relatively stable, the manufacturer of the bridge chip thinks whether there are any chips in the middle that have the minimum requirements for the receiving clock. Can you help confirm whether there are such requirements for 953 and 960?

  • 0 in reply to Amy Luo
    TI__Guru* 83920 points

    Hello Amy,

    can you provide the resolution and data type + frame rate used on the generated pattern on the DSI-CSI bridge?

    The min requirement for the UB953 input is 80Mbps/lane.

    The UB960 output CSI port has a min 368Mbps/lane

    Also, why the customer is using bridge to convert DSI to CSI then 953-960? They could use our DSI SER (DS90UB941AS) paired with the CSI DES (DS90UB940N) !!

  • 0 in reply to Hamzeh Jaradat
    Prodigy 50 points

    Hello Hamzeh,

    Thanks for your reply. I am the  customer that raised this question.

    We confiugred 2560x720@60/30fps pattern on DSI-CSI bridge while the data type is YUV422.

    Here are the timing and pixclk we used on pattern:

    // hfp, hs, hbp, hact, htotal, vfp, vs, vbp, vact, vtotal, pixclk(MHz), frame rate

    {48, 32, 80, 2560, 2720, 3, 6, 36, 720, 765, 124848, 60}, // 2560x720@60fps

    {176, 88, 296, 2560, 3120, 8, 10, 72, 720, 810, 75816, 30} // 2560x720@30fps

    How should we understand "The min requirement for the UB953 input is 80Mbps/lane."?

    Does that mean the MIPI CSI Clock should be larger than 320Mbps if we used 4 CSI lanes (4*80)?

  • 0 in reply to ju sheng
    TI__Guru* 83920 points

    Hello Ju,

    Yes, 80Mbps is the min datarate on a lane, means 4x80=320Mbps is the minimum total data rate can be transferred into the UB953.

     Actually the resolution you are using is completely compliant with the UB953 input. You have 1106Mbps for the 30fps, and 2212Mbps for the 60fps.

  • 0 in reply to Hamzeh Jaradat
    Prodigy 50 points

    Hello Hamzeh,

     

    Is it necessary to configure any register of UB953/UB960 when frame rate is changed from 60fps to 30fps?

    Thanks!

  • 0 in reply to ju sheng
    TI__Guru* 83920 points

    Hello Ju,

    No, there is no changes needed.

  • 0 in reply to Hamzeh Jaradat
    TI__Guru* 83920 points

    Can you please use our ALP Tool and capture the transmission channel using 30fps and using 60fps?