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XIO2001: Power-Down Sequence

Daniel Minors85
Prodigy 140 points
Part Number: XIO2001

From the datasheet the power down sequence is defined as below. There are no timing elements defined as per the power-up sequence.

Is it necessary that the REFCLK is stopped before the PCIR and Power rails are removed? Is there a time that the clock must be inactive before the voltages are removed.

  • 0
    TI__Guru* 91580 points

    Hi Daniel,

    REFCLK must be stopped to make sure there is no signal to power up the device through ESD structure - after VDD and PCIR are removed. However, timing for this has not been characterized. Looking at the power up sequence and power-down timing, i think 100uS can provide some margin as well.

    Regards ,, Nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 140 points

    Hi Nasser,

    Many thanks for the response. In my application VDD_33 and PCIR are supplied by the same rail that is powering the clock generation device a LMK00334RTVT. The REFOUT_EN  of the LMK00334RTVT device is pulled up to the same 3V3 rail to permanently enable that device. The clock supply and the bridge device supply rail will decay at the same rate. At some point before the rail is exhausted i expect the clock to stop being generated. Does this meet the requirements of the device or does the clock need to be removed before the VDD_33 and PCIR voltages go outside their operating range?

    Best Regards,

    Dan

  • 0 in reply to Daniel Minors85
    TI__Guru* 91580 points

    Hi Dan,

    Checked LMK data sheet and i suppose you don't have control over CLKOUT_EN# or CLKin_SEL to stop clock out. 

    Clock to be removed or stopped - before VDD_33 or PCIR goes away - is a good design practice and makes sense. However, part has not been characterized or checked under the scenario you are describing. I think probably it will work since LMK short circuit protection would kick in - even if REFCLK goes away after the VDD_33. However, this has not been characterized.

    Regards ,nasser