TCAN4550: CANBUS stops incrementing the RX byte values in ifconfig

Hi AyshaT,

What speed are you running the CAN at and what speed are you running the SPI at?

What device are you using to send SPI data?

Lastly, what does your CAN network look like? Is it one device in loopback or are there multiple devices?

Best,

Chris

Hi Chris,

     Thanks for your prompt reply.     
     What speed are you running the CAN at and what speed are you running the SPI at?
      1. CAN bitrate : 250kbps
      2. SPI speed : 5000000Hz
      3. CAN clock-frequency from external crystal : 40MHz
   
     What device are you using to send SPI data?
     Our HW board has one iMx8M Mini processor based SOM, 2 SPI interfaces and two TCAN4550 modules.
     Test 1: External Loopback Test with two TCAN4550 modules.(Reference Image-1)
         Data is sent and received between can0 and can1 of the same borad simultaneously.
         We are sending 1 byte from can0 to can1 and 2 bytes from can1 to can0.
         After a couple of transmission, it is observed that even though one CAN module sends the data packet but the other CAN module is not receiving it as described in my previous mail. Attached the script used for this test.

#!/bin/bash

# Initialize can0 and can 1 interfaces
ip link set can0 down
ip link set can1 down
ip link set can0 type can bitrate 2500000
ip link set can1 type can bitrate 2500000
ip link set can0 up
ip link set can1 up

# Initialize RX packet counts
can0rx=$(ifconfig can0 | awk 'match($0, /RX packets:([0-9]+)/, rx) {print rx[1]}')
can1rx=$(ifconfig can1 | awk 'match($0, /RX packets:([0-9]+)/, rx) {print rx[1]}')
can0rx_last=$can0rx-1
can1rx_last=$can1rx-1

pass=0
until [[ (can0rx -eq can0rx_last) || (can1rx -eq can1rx_last) ]]; 
#while [ 1 ]
do
    # Update variables
    let pass++
    can0rx_last=$can0rx
    can1rx_last=$can1rx

    # Send messages on both CAN interfaces
    cansend can0 520#10 & cansend can1 521#1010
    sleep 1
    
    # Get current RX packet counts
    can0rx=$(ifconfig can0 | awk 'match($0, /RX packets:([0-9]+)/, rx) {print rx[1]}')
    can1rx=$(ifconfig can1 | awk 'match($0, /RX packets:([0-9]+)/, rx) {print rx[1]}')
    echo "[Pass ${pass}]  can0:${can0rx}  can1:${can1rx}"
done

echo "CAN fault detected!"

     Test 2: TCAN4550 (can0) of our board with ECUSim2000 Simulator (Reference Image-2)
        The request is sent from can0 of our board to ECUSim2000 simulator and response is received from Simulator.
        After some amount of transmission, it is observed that even though our CAN module sends the data packet but we are getting time out error.
        That means we are not getting response from Simulator and it got stopped by some reasons.

     what does your CAN network look like? Is it one device in loopback or are there multiple devices?
     I have attached the images for your reference. One test is conducted with extrenal loop back between two CAN modules of same board
     and other test is conducted between one CAN module and simulator.  

Best regards,
AyshaT

AyshaT,

Depending on your SPI Driver it is entirely possible that the SPI data is being sent too fast and is causing an overflow error in the FIFO of your MCU. Can you verify if your FIFO is filled up when the RX bytes stops incrementing? 

If this is the case the error that is thrown by your FIFO overflowing could cause the TCAN4550 to stop sending data.

Best,

Chris

Hi Chris,

• The value of Interrupt register 1050

          When data is in RX register: 3
          When data is in TX register: 1800

         This indicates the RX and TX is not overflow.I have attached the output of the script( shared in previous mail) with the register values captured.

root@iWave-G39H:~# ./can_test.sh 
[  140.472640] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.485478] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.496864] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.508525] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.520008] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.528669] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=0
[  140.536943] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=3
[  140.545325] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=3
[  140.553390] [DEBUG_NEW] tcan4x5x_read_reg reg=10,  priv->reg_offset + reg = 1010, val=80
[  140.561966] [DEBUG_NEW] tcan4x5x_read_reg reg=1c,  priv->reg_offset + reg = 101c, val=41a03
[  140.570344] [DEBUG-NEW] m_can_set_bittiming kkk=41a03
[  140.575476] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=3
[  140.583861] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=0
[  140.629823] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.638681] IPv6: ADDRCONF(NETDEV_CHANGE): can0: link becomes ready
[  140.645089] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.653732] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.662368] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=0
[  140.670690] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=3
[  140.679037] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=3
[  140.687163] [DEBUG_NEW] tcan4x5x_read_reg reg=10,  priv->reg_offset + reg = 1010, val=80
[  140.697000] [DEBUG_NEW] tcan4x5x_read_reg reg=1c,  priv->reg_offset + reg = 101c, val=41a03
[  140.705378] [DEBUG-NEW] m_can_set_bittiming kkk=41a03
[  140.710770] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=3
[  140.719429] [DEBUG_NEW] tcan4x5x_read_reg reg=18,  priv->reg_offset + reg = 1018, val=0
[  140.766051] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[  140.791789] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  140.791792] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  140.791845] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  140.799913] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  140.808083] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=0
[  140.816134] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=0
[  140.824132] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10006
[  140.824279] [DEBUG-NEW]  m_can_isr start can1
[  140.824281] [DEBUG-NEW]  m_can_isr start can0
[  140.824342] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  140.824344] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  140.824345] [DEBUG-NEW] 1.m_can_isr 3
[  140.824346] [DEBUG-NEW] 1.m_can_isr 1800
[  140.824594] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=10001
[  140.824636] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=10001
[  140.824641] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  140.824643] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  140.824704] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  140.824737] NOHZ: local_softirq_pending 08
[  140.824739] NOHZ: local_softirq_pending 08
[  140.824753] NOHZ: local_softirq_pending 08
[  140.824757] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=10001
[  140.824760] NOHZ: local_softirq_pending 08
[  140.824772] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  140.824778] [DEBUG-NEW] m_can_isr end can0
[  140.824979] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=10100
[  140.825020] [DEBUG-NEW] m_can_rx_peripheral kk = 1
[  140.825022] [DEBUG-NEW] m_can_isr end can1
[  140.825028] [DEBUG-NEW]  m_can_isr start can1
[  140.825070] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  140.832270] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10006
[  140.832481] [DEBUG-NEW]  m_can_isr start can0
[  140.832482] [DEBUG-NEW]  m_can_isr start can1
[  140.832534] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  140.832536] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  140.832537] [DEBUG-NEW] 1.m_can_isr 3
[  140.832538] [DEBUG-NEW] 1.m_can_isr 1800
[  140.832829] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=10001
[  140.832895] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=10001
[  140.832897] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  140.832899] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  140.832943] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  140.832989] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=10001
[  140.833070] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  140.833076] [DEBUG-NEW] m_can_isr end can1
[  140.833195] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=10100
[  140.833235] [DEBUG-NEW] m_can_rx_peripheral kk = 2
[  140.833237] [DEBUG-NEW] m_can_isr end can0
[  141.662122] IPv6: ADDRCONF(NETDEV_CHANGE): can1: link becomes ready
[  141.668553] [DEBUG_NEW] tcan4x5x_read_reg reg=40,  priv->reg_offset + reg = 1040, val=0
[Pass 1]  can0:1  can1:1
[  141.816070] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  141.816232] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  141.824564] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  141.832929] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  141.841472] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  141.849799] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  141.858000] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20106
[  141.858232] [DEBUG-NEW]  m_can_isr start can1
[  141.858233] [DEBUG-NEW]  m_can_isr start can0
[  141.858297] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  141.858299] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  141.858300] [DEBUG-NEW] 1.m_can_isr 3
[  141.858301] [DEBUG-NEW] 1.m_can_isr 1800
[  141.858568] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=20101
[  141.858612] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  141.858614] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=20101
[  141.858615] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  141.858666] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  141.858715] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=20101
[  141.858783] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  141.858790] [DEBUG-NEW] m_can_isr end can1
[  141.858935] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=20200
[  141.858979] [DEBUG-NEW] m_can_rx_peripheral kk = 3
[  141.858981] [DEBUG-NEW] m_can_isr end can0
[  141.866271] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20106
[  141.866494] [DEBUG-NEW]  m_can_isr start can1
[  141.866496] [DEBUG-NEW]  m_can_isr start can0
[  141.866553] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  141.866555] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  141.866556] [DEBUG-NEW] 1.m_can_isr 3
[  141.866557] [DEBUG-NEW] 1.m_can_isr 1800
[  141.866841] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=20101
[  141.866884] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  141.866887] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=20101
[  141.866888] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  141.866934] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  141.866977] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=20101
[  141.867029] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  141.867035] [DEBUG-NEW] m_can_isr end can0
[  141.867188] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=20200
[  141.867229] [DEBUG-NEW] m_can_rx_peripheral kk = 4
[  141.867233] [DEBUG-NEW] m_can_isr end can1
[Pass 2]  can0:2  can1:2
[  142.838847] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  142.847270] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  142.855678] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  142.855752] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  142.872645] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  142.872693] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  142.889276] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30206
[  142.889312] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30206
[  142.897944] [DEBUG-NEW]  m_can_isr start can0
[  142.906024] [DEBUG-NEW]  m_can_isr start can1
[  142.906093] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1803
[  142.923051] [DEBUG-NEW] 1.m_can_isr 1803
[  142.923056] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1803
[  142.927265] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  142.935251] [DEBUG-NEW] 1.m_can_isr 1803
[  142.947215] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  142.952515] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  142.960771] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=30201
[  142.969362] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=30300
[  142.977803] [DEBUG-NEW] m_can_rx_peripheral kk = 5
[  142.982625] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  142.982662] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=30201
[  142.990657] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  142.999067] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=30201
[  143.012773] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  143.021165] [DEBUG-NEW] m_can_isr end can1
[  143.021425] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  143.033774] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=30201
[  143.043224] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=30300
[  143.051892] [DEBUG-NEW] m_can_rx_peripheral kk = 6
[  143.056750] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=30201
[  143.065167] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=30201
[  143.073912] NOHZ: local_softirq_pending 08
[  143.078336] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  143.086716] [DEBUG-NEW] m_can_isr end can0
[Pass 3]  can0:3  can1:3
[  143.860831] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  143.860833] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  143.860885] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  143.870487] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  143.878461] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  143.886756] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  143.894751] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40306
[  143.894984] [DEBUG-NEW]  m_can_isr start can1
[  143.895046] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  143.895048] [DEBUG-NEW] 1.m_can_isr 3
[  143.895321] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  143.895323] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  143.895365] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  143.895409] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=40301
[  143.895624] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=40400
[  143.895665] [DEBUG-NEW] m_can_rx_peripheral kk = 7
[  143.895667] [DEBUG-NEW] m_can_isr end can1
[  143.903077] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40306
[  143.903287] [DEBUG-NEW]  m_can_isr start can1
[  143.903339] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  143.903341] [DEBUG-NEW] 1.m_can_isr 1800
[  143.903593] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=40301
[  143.903632] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=40301
[  143.903762] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  143.903768] [DEBUG-NEW] m_can_isr end can1
[  143.911237] [DEBUG-NEW]  m_can_isr start can0
[  143.911299] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1803
[  144.049006] [DEBUG-NEW] 1.m_can_isr 1803
[  144.053576] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  144.061595] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  144.067182] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  144.075445] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=40301
[  144.084100] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=40400
[  144.092513] [DEBUG-NEW] m_can_rx_peripheral kk = 8
[  144.097367] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=40301
[  144.105776] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=40301
[  144.114240] NOHZ: local_softirq_pending 08
[  144.118392] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  144.126753] [DEBUG-NEW] m_can_isr end can0
[Pass 4]  can0:4  can1:4
[  144.890300] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  144.890302] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  144.890357] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  144.899168] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  144.907505] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  144.915905] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  144.924179] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50406
[  144.924405] [DEBUG-NEW]  m_can_isr start can0
[  144.924407] [DEBUG-NEW]  m_can_isr start can1
[  144.924467] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  144.924469] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  144.924470] [DEBUG-NEW] 1.m_can_isr 3
[  144.924471] [DEBUG-NEW] 1.m_can_isr 1800
[  144.924722] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=50401
[  144.924761] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  144.924763] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=50401
[  144.924765] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  144.924814] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  144.924867] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=50401
[  144.924946] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  144.924952] [DEBUG-NEW] m_can_isr end can1
[  144.925076] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=50500
[  144.925117] [DEBUG-NEW] m_can_rx_peripheral kk = 9
[  144.925119] [DEBUG-NEW] m_can_isr end can0
[  144.932486] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50406
[  144.932714] [DEBUG-NEW]  m_can_isr start can0
[  144.932716] [DEBUG-NEW]  m_can_isr start can1
[  144.932774] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  144.932775] [DEBUG-NEW] 1.m_can_isr 1800
[  144.932778] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  144.932779] [DEBUG-NEW] 1.m_can_isr 3
[  144.933026] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=50401
[  144.933069] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=50401
[  144.933158] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  144.933160] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  144.933169] NOHZ: local_softirq_pending 08
[  144.933171] NOHZ: local_softirq_pending 08
[  144.933181] NOHZ: local_softirq_pending 08
[  144.933184] NOHZ: local_softirq_pending 08
[  144.933199] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  144.933206] [DEBUG-NEW] m_can_isr end can0
[  144.933209] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  144.933252] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=50401
[  144.933888] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=50500
[  144.933935] [DEBUG-NEW] m_can_rx_peripheral kk = 10
[  144.933937] [DEBUG-NEW] m_can_isr end can1
[Pass 5]  can0:5  can1:5
[  145.922747] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  145.922749] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  145.922798] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  145.939560] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  145.956532] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  145.964968] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60506
[  145.973370] [DEBUG-NEW]  m_can_isr start can1
[  145.973664] [DEBUG-NEW]  m_can_isr start can0
[  145.982178] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  145.990455] [DEBUG-NEW] 1.m_can_isr 1800
[  145.994798] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  146.002826] [DEBUG-NEW] 1.m_can_isr 3
[  146.006562] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a2
[  146.006843] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  146.014852] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=60501
[  146.022850] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  146.036515] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=60501
[  146.045223] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  146.045287] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  146.061801] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  146.061836] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=60501
[  146.070163] [DEBUG-NEW] m_can_isr end can0
[  146.078523] [DEBUG-NEW]  m_can_isr start can0
[  146.086998] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  146.087215] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=60600
[  146.095010] [DEBUG-NEW] 1.m_can_isr 3
[  146.107103] [DEBUG-NEW] m_can_rx_peripheral kk = 11
[  146.111999] [DEBUG-NEW] m_can_isr end can1
[  146.116122] [DEBUG-NEW]  m_can_isr start can1
[  146.120539] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  146.128825] [DEBUG-NEW] 1.m_can_isr 1800
[  146.132993] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=60501
[  146.141430] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=60501
[  146.149928] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  146.158299] [DEBUG-NEW] m_can_isr end can1
[  146.162715] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  146.170733] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  146.175766] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  146.184018] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=60501
[  146.192611] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=60600
[  146.201033] [DEBUG-NEW] m_can_rx_peripheral kk = 12
[  146.205927] [DEBUG-NEW] m_can_isr end can0
[Pass 6]  can0:6  can1:6
[  146.947003] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  146.947212] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  146.963791] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  146.963829] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  146.980758] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  146.989153] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=606
[  146.997361] [DEBUG-NEW]  m_can_isr start can0
[  147.001749] [DEBUG-NEW]  m_can_isr start can1
[  147.006165] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  147.014449] [DEBUG-NEW] 1.m_can_isr 1800
[  147.014743] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  147.018642] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=70601
[  147.026386] [DEBUG-NEW] 1.m_can_isr 3
[  147.038468] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=70601
[  147.046971] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  147.055000] [DEBUG-NEW] m_can_isr end can1
[  147.059692] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=0
[  147.068142] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  147.076161] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  147.081544] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=718
[  147.081844] [DEBUG-NEW]  m_can_isr start can1
[  147.094140] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=70601
[  147.094177] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  147.110524] [DEBUG-NEW] 1.m_can_isr 3
[  147.114478] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  147.114536] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  147.122502] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  147.135530] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  147.143775] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=70601
[  147.152360] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=70700
[  147.160769] [DEBUG-NEW] m_can_rx_peripheral kk = 13
[  147.165672] [DEBUG-NEW] m_can_isr end can1
[  147.170445] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=70700
[  147.178862] [DEBUG-NEW] m_can_rx_peripheral kk = 14
[  147.183757] [DEBUG-NEW] m_can_isr end can0
[  147.187882] [DEBUG-NEW]  m_can_isr start can0
[  147.192322] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  147.200602] [DEBUG-NEW] 1.m_can_isr 1800
[  147.204801] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=70601
[  147.213212] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=70601
[  147.221821] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  147.229856] [DEBUG-NEW] m_can_isr end can0
[Pass 7]  can0:7  can1:7
[  147.969938] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  147.969947] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  147.978086] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  147.986058] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  147.994266] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  148.002446] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  148.010519] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10006
[  148.010753] [DEBUG-NEW]  m_can_isr start can1
[  148.010804] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  148.010805] [DEBUG-NEW] 1.m_can_isr 3
[  148.011086] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  148.011088] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  148.011130] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  148.011173] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=80701
[  148.011384] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=80800
[  148.011425] [DEBUG-NEW] m_can_rx_peripheral kk = 15
[  148.011427] [DEBUG-NEW] m_can_isr end can1
[  148.018680] [DEBUG-NEW]  m_can_isr start can0
[  148.018740] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  148.102563] [DEBUG-NEW] 1.m_can_isr 1800
[  148.106955] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10006
[  148.107113] [DEBUG-NEW]  m_can_isr start can1
[  148.119757] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  148.128098] [DEBUG-NEW] 1.m_can_isr 1800
[  148.132301] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=80701
[  148.132341] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=80701
[  148.140719] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=80701
[  148.157407] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=80701
[  148.157538] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  148.174131] [DEBUG-NEW] m_can_isr end can1
[  148.178630] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  148.187017] [DEBUG-NEW] m_can_isr end can0
[  148.191149] [DEBUG-NEW]  m_can_isr start can0
[  148.195859] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  148.203878] [DEBUG-NEW] 1.m_can_isr 3
[  148.211395] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  148.219414] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  148.224718] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  148.233260] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=80701
[  148.242142] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=80800
[  148.250842] [DEBUG-NEW] m_can_rx_peripheral kk = 16
[  148.255735] [DEBUG-NEW] m_can_isr end can0
[Pass 8]  can0:8  can1:8
[  148.991761] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  148.991936] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  149.000452] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  149.008752] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=10107
[  149.017336] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  149.025677] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  149.033902] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20106
[  149.034120] [DEBUG-NEW]  m_can_isr start can1
[  149.034173] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  149.034175] [DEBUG-NEW] 1.m_can_isr 1800
[  149.034415] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=90801
[  149.034458] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=90801
[  149.034598] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  149.034604] [DEBUG-NEW] m_can_isr end can1
[  149.042061] [DEBUG-NEW]  m_can_isr start can0
[  149.042123] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  149.108476] [DEBUG-NEW] 1.m_can_isr 3
[  149.112407] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20106
[  149.112526] [DEBUG-NEW]  m_can_isr start can1
[  149.125203] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  149.133241] [DEBUG-NEW] 1.m_can_isr 3
[  149.136935] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  149.137244] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  149.145213] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  149.158467] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  149.158480] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  149.163502] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  149.179822] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=90801
[  149.179855] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=90801
[  149.196822] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=90900
[  149.205238] [DEBUG-NEW] m_can_rx_peripheral kk = 17
[  149.210137] [DEBUG-NEW] m_can_isr end can1
[  149.214682] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=90900
[  149.223093] [DEBUG-NEW] m_can_rx_peripheral kk = 18
[  149.227985] [DEBUG-NEW] m_can_isr end can0
[  149.232113] [DEBUG-NEW]  m_can_isr start can0
[  149.236537] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  149.244821] [DEBUG-NEW] 1.m_can_isr 1800
[  149.249005] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=90801
[  149.257425] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=90801
[  149.266225] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  149.274607] [DEBUG-NEW] m_can_isr end can0
[Pass 9]  can0:9  can1:9
[  150.013653] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  150.013832] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  150.022272] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  150.030678] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=20207
[  150.039187] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  150.047601] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  150.055775] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30206
[  150.056007] [DEBUG-NEW]  m_can_isr start can1
[  150.056062] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  150.056064] [DEBUG-NEW] 1.m_can_isr 1800
[  150.056299] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=a0901
[  150.056342] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=a0901
[  150.056484] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  150.056489] [DEBUG-NEW] m_can_isr end can1
[  150.063987] [DEBUG-NEW]  m_can_isr start can0
[  150.122689] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  150.130713] [DEBUG-NEW] 1.m_can_isr 3
[  150.134628] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30206
[  150.134747] [DEBUG-NEW]  m_can_isr start can1
[  150.147474] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  150.155564] [DEBUG-NEW] 1.m_can_isr 3
[  150.159261] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  150.159265] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  150.167850] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  150.180803] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  150.180810] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  150.185828] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  150.202195] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=a0901
[  150.210773] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=a0a00
[  150.210862] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=a0901
[  150.219184] [DEBUG-NEW] m_can_rx_peripheral kk = 19
[  150.232401] [DEBUG-NEW] m_can_isr end can1
[  150.236659] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=a0a00
[  150.245073] [DEBUG-NEW] m_can_rx_peripheral kk = 20
[  150.249965] [DEBUG-NEW] m_can_isr end can0
[  150.254086] [DEBUG-NEW]  m_can_isr start can0
[  150.258788] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  150.267066] [DEBUG-NEW] 1.m_can_isr 1800
[  150.271254] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=a0901
[  150.279678] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=a0901
[  150.288476] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  150.296858] [DEBUG-NEW] m_can_isr end can0
[Pass 10]  can0:10  can1:10
[  151.039548] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  151.047988] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  151.048047] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  151.064760] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=30307
[  151.073314] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  151.073391] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  151.089968] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40306
[  151.090005] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40306
[  151.098344] [DEBUG-NEW]  m_can_isr start can0
[  151.106750] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1803
[  151.111109] [DEBUG-NEW]  m_can_isr start can1
[  151.119361] [DEBUG-NEW] 1.m_can_isr 1803
[  151.127757] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1803
[  151.136040] [DEBUG-NEW] 1.m_can_isr 1803
[  151.140288] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  151.148307] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  151.153590] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  151.161846] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=b0a01
[  151.170439] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=b0b00
[  151.178858] [DEBUG-NEW] m_can_rx_peripheral kk = 21
[  151.183800] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=b0a01
[  151.192216] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=b0a01
[  151.200735] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  151.200897] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  151.209108] [DEBUG-NEW] m_can_isr end can1
[  151.221215] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  151.226785] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  151.235326] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=b0a01
[  151.244199] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=b0b00
[  151.252606] [DEBUG-NEW] m_can_rx_peripheral kk = 22
[  151.257846] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=b0a01
[  151.266543] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=b0a01
[  151.275324] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  151.283703] [DEBUG-NEW] m_can_isr end can0
[Pass 11]  can0:11  can1:11
[  152.062410] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  152.071086] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  152.079482] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  152.079528] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=40407
[  152.096406] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  152.096465] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  152.113039] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50406
[  152.113128] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50406
[  152.121415] [DEBUG-NEW]  m_can_isr start can0
[  152.134150] [DEBUG-NEW]  m_can_isr start can1
[  152.134155] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1803
[  152.138566] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1803
[  152.146780] [DEBUG-NEW] 1.m_can_isr 1803
[  152.158980] [DEBUG-NEW] 1.m_can_isr 1803
[  152.163161] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  152.163236] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  152.171179] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  152.184428] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  152.184723] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  152.189710] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  152.206082] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=c0b01
[  152.214650] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=c0c00
[  152.214752] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=c0b01
[  152.223071] [DEBUG-NEW] m_can_rx_peripheral kk = 23
[  152.236304] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=c0b01
[  152.244717] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=c0b01
[  152.253243] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  152.261621] [DEBUG-NEW] m_can_isr end can1
[  152.266784] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=c0c00
[  152.275238] [DEBUG-NEW] m_can_rx_peripheral kk = 24
[  152.280188] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=c0b01
[  152.288615] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=c0b01
[  152.297105] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  152.305491] [DEBUG-NEW] m_can_isr end can0
[Pass 12]  can0:12  can1:12
[  153.084029] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  153.084032] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  153.084091] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  153.092986] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=50507
[  153.102172] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  153.109840] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  153.117922] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60506
[  153.118162] [DEBUG-NEW]  m_can_isr start can1
[  153.118217] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  153.118219] [DEBUG-NEW] 1.m_can_isr 3
[  153.118510] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  153.118512] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  153.118556] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  153.118600] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=d0c01
[  153.118824] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=d0d00
[  153.118866] [DEBUG-NEW] m_can_rx_peripheral kk = 25
[  153.118868] [DEBUG-NEW] m_can_isr end can1
[  153.126111] [DEBUG-NEW]  m_can_isr start can0
[  153.126180] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  153.218229] [DEBUG-NEW] 1.m_can_isr 1800
[  153.222507] [DEBUG-NEW]  m_can_isr start can1
[  153.226882] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  153.235315] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  153.243609] [DEBUG-NEW] 1.m_can_isr 1800
[  153.243618] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=d0c01
[  153.247878] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=d0c01
[  153.264279] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=d0c01
[  153.264316] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=d0c01
[  153.281149] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  153.289520] [DEBUG-NEW] m_can_isr end can1
[  153.293785] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  153.302169] [DEBUG-NEW] m_can_isr end can0
[  153.306595] [DEBUG-NEW]  m_can_isr start can0
[  153.311307] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  153.319321] [DEBUG-NEW] 1.m_can_isr 3
[  153.323851] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=0
[  153.331877] [DEBUG-NEW] m_can_rx_handler irqstatus=3
[  153.336908] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  153.345427] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=d0c01
[  153.354566] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=d0d00
[  153.362971] [DEBUG-NEW] m_can_rx_peripheral kk = 26
[  153.367868] [DEBUG-NEW] m_can_isr end can0
[Pass 13]  can0:13  can1:13
[  154.123354] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  154.123358] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  154.123414] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  154.140198] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=60607
[  154.148822] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  154.165387] [DEBUG_NEW] tcan4x5x_read_reg reg=820,  priv->reg_offset + reg = 1820, val=4a0
[  154.165390] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=606
[  154.165612] [DEBUG-NEW]  m_can_isr start can1
[  154.165892] [DEBUG-NEW]  m_can_isr start can0
[  154.182035] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=3
[  154.186272] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  154.190571] [DEBUG-NEW] 1.m_can_isr 3
[  154.198631] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  154.206887] [DEBUG-NEW] 1.m_can_isr 1800
[  154.207134] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=e0d01
[  154.230925] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=e0d01
[  154.239385] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  154.239445] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  154.247661] [DEBUG-NEW] m_can_rx_handler irqstatus=1803
[  154.260913] [DEBUG-NEW] m_can_isr end can1
[  154.261212] [DEBUG_NEW] tcan4x5x_read_reg reg=44,  priv->reg_offset + reg = 1044, val=708
[  154.273276] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=e0d01
[  154.282124] [DEBUG_NEW] tcan4x5x_read_reg reg=a4,  priv->reg_offset + reg = 10a4, val=e0e00
[  154.290533] [DEBUG-NEW] m_can_rx_peripheral kk = 27
[  154.295427] [DEBUG-NEW] m_can_isr end can0
[  154.299546] [DEBUG-NEW]  m_can_isr start can0
[  154.304228] [DEBUG_NEW] tcan4x5x_read_reg reg=50,  priv->reg_offset + reg = 1050, val=1800
[  154.312504] [DEBUG-NEW] 1.m_can_isr 1800
[  154.316691] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=e0d01
[  154.325102] [DEBUG_NEW] tcan4x5x_read_reg reg=f4,  priv->reg_offset + reg = 10f4, val=e0d01
[  154.334194] [DEBUG_NEW] tcan4x5x_read_reg reg=c4,  priv->reg_offset + reg = 10c4, val=7
[  154.342232] [DEBUG-NEW] m_can_isr end can0
[Pass 14]  can0:14  can1:13
CAN fault detected!

• The interrupt gpios are setting low and high when transfer happens between can0 and can1. But when fault occurs, the interrupt gpio is in low state in one of the CAN device(observed in CRO). The gpio remains low till the can device is set down.
• The processor stops receiving from the controller when fault occurs from one of the CAN device. What's the cause for this?

Best regards,
Aysha T

Hi Aysha,

Can you provide some scope shots of the SPI lines? We would like to see how efficient the SPI driver is. Also what version of the driver are you using?

The interrupt being held low shows that there is some timing issue that is causing the driver to get stuck.

Best,

Chris

Hi Chris ,

I am using tcan4x5x driver back ported for linux 4.14.98 version. I have attached the SPI lines output captured from CRO.

CAN0 Observations:

• CS and SCLK

• SCLK and MOSI

• SCLK and MISO

CAN1 Observations:

• CS and SCLK

• SCLK and MOSI

• SCLK and MISO

FYI: I had observed the same issue in tcan4x5x driver of kernel 5.4.70.

Best regards,
Aysha T

Hi Chris,

In addition to previous reply I have attached SPI data lines captured from Saleae Logic Analyzer when fault occurs.

CAN0 SPI lines

CAN1 SPI lines

I have also noticed that when the fault occurs the register contains,
            16'h0820=82 (in hexadecimal)
            16'h0824=3 (in hexadecimal)
This results GLOBALERR (Global Error (Any Fault)).

What is the cause for this? How can it be resolved?

Regards,
Aysha T

Hi Chris,

I have checked other TI replies (tcan4550-problem-with-sending-back-ack-data-timing-isue-and-globalerr) regarding GLOBAL ERROR and made below workarounds,

•  Set SPI to maximum frequency:  So I set the SPI frequency to 18MHz(max value). Even the fault has occured

•  Set ANFS[1:0] and ANFE[1:0] bit fields of Global Filter configuration register as b'10. The fault has occured even after setting ANFS and ANFE as 10.

We had added below lines of code under routine m_can_isr() in m_can.c file. After this changes the script continues its execution without any stop.

        ir = m_can_read(cdev, M_CAN_IR);
        if (!ir){
                return IRQ_HANDLED;
        }
        if ((ir & IR_RF0W) || (ir & IR_ERR_ALL_30X)) {
                cdev->irqstatus = ir;
                m_can_disable_all_interrupts(cdev);
                if (!cdev->is_peripheral)
                        napi_schedule(&cdev->napi);
                else
                        m_can_rx_peripheral(dev);
        }

The entire routine m_can_isr is attached below.

static irqreturn_t m_can_isr(int irq, void *dev_id)
{
        struct net_device *dev = (struct net_device *)dev_id;
        struct m_can_classdev *cdev = netdev_priv(dev);
        struct net_device_stats *stats = &dev->stats;
        u32 ir;

        ir = m_can_read(cdev, M_CAN_IR);
        if (!ir)
                return IRQ_NONE;

        /* ACK all irqs */
        if (ir & IR_ALL_INT)
                m_can_write(cdev, M_CAN_IR, ir);

        if (cdev->ops->clear_interrupts)
                cdev->ops->clear_interrupts(cdev);

        /* schedule NAPI in case of
         * - rx IRQ
         * - state change IRQ
         * - bus error IRQ and bus error reporting
         */
        if ((ir & IR_RF0W) || (ir & IR_ERR_ALL_30X)) {
                cdev->irqstatus = ir;
                m_can_disable_all_interrupts(cdev);
                if (!cdev->is_peripheral)
                        napi_schedule(&cdev->napi);
                else
                        m_can_rx_peripheral(dev);
        }

        if (cdev->version == 30) {
                if (ir & IR_TC) {
                        /* Transmission Complete Interrupt*/
                        stats->tx_bytes += can_get_echo_skb(dev, 0);
                        stats->tx_packets++;

                        can_led_event(dev, CAN_LED_EVENT_TX);
                        netif_wake_queue(dev);
                }
        } else  {
                if (ir & IR_TEFN) {
                        /* New TX FIFO Element arrived */
                        m_can_echo_tx_event(dev);
                        can_led_event(dev, CAN_LED_EVENT_TX);
                        if (netif_queue_stopped(dev) &&
                            !m_can_tx_fifo_full(cdev))
                                netif_wake_queue(dev);
                }
        }

        ir = m_can_read(cdev, M_CAN_IR);
        if (!ir){
                return IRQ_HANDLED;
        }
        if ((ir & IR_RF0W) || (ir & IR_ERR_ALL_30X)) {
                cdev->irqstatus = ir;
                m_can_disable_all_interrupts(cdev);
                if (!cdev->is_peripheral)
                        napi_schedule(&cdev->napi);
                else
                        m_can_rx_peripheral(dev);
        }

        return IRQ_HANDLED;
}

Is the changes made in m_can_isr() is correct? Will this leads to any other problem?

Best regards,
Aysha T

Hi Chris,

Hope you are doing good.
As I have faced the issue even after adding the set of lines mentioned in previous reply. The test went on for about 13hours.
Please look forward to resolve this fault.

Best regards,
Aysha T

Ayasha,

Thanks for the detailed information. I'm not very familiar with how the linux driver handles these situations, but I am familiar with using this device in embedded devices.

What I think might be happening is that an interrupt is being missed by the SPI0 device due to some timing event. I've seen a race condition like this happen in embedded drivers where the interrupt routine assumes that the nINT pin is cleared before exiting instead of confirming it. So when it exits the ISR, since it was edge triggered, there never is another edge, and the driver assumes there's nothing pending (even though the nINT line is held low).

I'll illustrate below. Normally, I would recommend that clearing the interrupts be done at the end of the ISR routine if using edge trigger for ISR. The last steps for the ISR would be

1) Check to see if any new interrupts came in while handling the previous one. (Checking rxf0s to see how many messages are still unread in the incoming mailbox)

2) If not, then clear interrupts

You can also clear interrupts at the beginning and simply recheck pending interrupts at the end. I'd expect to see the following behavior.

Where I have seen this go wrong is with high bus loads, where it's possible that the ISR routine takes long enough that it's possible for new interrupts to come in while handling a previous ISR (which is why people suggest speeding up SPI, it's a band aid to this condition).

If an additional interrupt comes in and you clear the interrupt at the beginning of the ISR, the device generates an edge WHILE the CPU is in the ISR. If the ISR doesn't check that there any any pending interrupts (either via checkign the nINT pin state (recommended) or by checking the interrupt register), then the ISR might exit while the nINT pin is still low. If the ISR is edge-based, then since any further interrupts will NOT toggle the pin, the CPU will never see an edge, and think the device is idle. This matches your behavior.

If we look at your scope shot during the fault, we see the potential for somethign like this to occur. I drew in red where there's a LONG pause (probably due to a higher priority ISR firing). Underneath, I drew what the nINT pin is likely doing.

In the end, the driver SHOULD be able to handle receiving another message/interrupt while it's servicing a previous one. I'm not familiar enough with the linux driver to be sure that's what's happening.

You mentioned in your last post that you modified the ISR to read MCAN_IR and then clear any interrupts if they are pending, which appears to have fixed most of your problems, but keep in mind that this would technically make the window where you might drop a message smaller, but does not eliminate the condition. Sometimes a level-trigger is better for this, because if the device exits the ISR, but the nINT pin is still low, the ISR will re-trigger, and look for pending interrupts. The fact that this tweak to the driver improved this situation further leads me to think that this condition i've illustrated is what's happening. We should make this driver able to handle this situation gracefully to ensure reliable communication in high-bus loads.

Questions:

1) In your device tree file, is your nINT pin set up as edge triggered or level triggered?

2) Can you grab a scope shot of this fault occuring, but grabbing 1: CANH or CANL (doesn't matter), 2: nCS (so we can see SPI activity), 3: SCLK (same reason), 4: nINT. With these 4 signals, we should be able to verify if a missed INT is what's happening and can dig into it further.

3) I see you mentioned you back ported the driver from 5.4 and mentioned the issue was seen when running 5.4. I know that was the initial version upstreamed, and was later changed (in 5.12 i think) to essentially be a wrapper for the MCAN driver. I do not know for sure if such a condition was fixed in the 5.12+ kernel version. Any chance you can run 5.15 and test the same situation? I realize it might not be possible due to your device, but would be interesting for us to note that earlier versions of the linux driver have this race condition that might have been fixed in later versions.

Hi Jonathan,

Thankyou for your response.

We are currently working through the suggestions on clearing the interrupt before and after interrupt handle. We will update to this on next mail.

Inresponse to your questions:
In your device tree file, is your nINT pin set up as edge triggered or level triggered?
We have configured as IRQ_TYPE_NONE ( default, unspecified type ) in dts file. I have tested with IRQ_TYPE_EDGE_RISING and IRQ_TYPE_LEVEL_HIGH . But the fault had occured.

Attached the scope shot captured. We could capture below data(CANL) before the fault occured.

Working on backport on tcan driver of 5.15 kernel to 4.14 has more functional dependencies.

Best regards,
Aysha T

You mention you tried edge_rising and level_high. The nINT pin is an active_low signal. Have you tried IRQ_TYPE_LEVEL_LOW? LEVEL_HIGH would make the IRQ fire whenever there was NOT an interrupt, and would not fire when there was an interrupt.

You should be using eitehr EDGE_FALLING (high to low transition is an interrupt event) or LEVEL_LOW (low signal on nINT = pending interrupt).

In the scope shot, can you try zooming out more. I'm not as concerned with what the data is, mainly just wanting to see when SPI and CAN are toggling relative to when the fault occurs. I don't see an nINT transition in your scope shot. Your scale is 5V, so I assume you're using VIO at 2.5V, and that nINT is actually high in that photo?