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Hi team,
I got a question from customer.
"We have situation in which a AM26C32 is powered and the inputs terminated by 100ohm. However, the differential driver (AM26LV31E) is unpowered for some period of time after the AM26C32. Can you help us to understand if the device fail-safe under these conditions will prevent the output from glitching (moment low condition) either during the unpowered time of the differential driver or while the differential driver is being powered-up?"
Thank you very much for your help.
Best regards,
Hi Zhonghui,
So there aren't really "fail-safe" features on this device due to its age. So with the current setup with the bus being opened on the driver side (due to it "floating" in the off position) - if during this time a valid differential voltage is read at the receiver there could be a glitch at the output which could occur at power off and upon powering up.
Now there are a couple work-arounds to help avoid problems in this situation:
1. Add Fail-Safe Biasing resistors:
This essentially can help in a applications such as this - the fs resistor value is set so that you can set the "resting" voltage on the bus which also will change the hysteresis for the differential inputs. The driver chosen needs to be able to handle the bus voltage when it is powered off - for this driver the abs max voltage on the output is 6V - so it should be okay to use this type of solution.
2. Keep the AM26C32 disabled until AM26LV31E is powered up. The driver will not produce signals while its off or ramping up that will "damage" the AM26C32. So by utilizing the G/G* pins the the AM26C32 can be powered up but disabled and then can be enabled when the driver comes up to proper operating power.
So each of these choices is possible and they each have benefits and draw backs and depending on the system one may be easier to implement over the other one.
If you have any other questions please let me know!
Best,
Parker Dodson
Hi Parker,
Thank you for your response. I do have a question on what the datasheet states about fail-safe for this component "Fail-safe design specifies that if the inputs are open, the outputs always are high". Will you clarify the statement for me please? Also, when you say "due to its age", are there newer TI parts (5V and same footprint) that do have an internal fail-safe?
Best regards,
"Open" means that the inputs are not connected to anything. The termination resistor, if present, will short the inputs together.
Parts with better internal fail-safe will say in their datasheet that they protect against a shorted or idle bus (they have a defined state when the differential input voltage is 0 V). But there are no modern four-channel receivers; you have to implement one of the workarounds mentioned by Parker, or use entirely different transceivers.
Hi Zhonghui,
Clemens is correct on the interpretation of the internal fail-safe design statement.
That being said - yes when I said age I was referring to this device was released originally in December of 1990 and at that time internal fail safe protection wasn't a feature that was really offered. However Clemens is correct - there aren't modern 4 channel receivers that have the internal failsafe - using the bus protection mentioned above is a perfectly acceptable work-around to achieving functionality in the system.
If you have any other questions please let me know!
Best,
Parker Dodson