SN65DSI84: [LVDS bridge] TI SN65DSI84 LVDS bridge question

Jimmy

Are you putting the SOC into ULPS state?

Once the SOC is enabled, You may need to wait for a minimum of 3 ms. and then set the DSI94 SOFT_RESET bit (CSR 0x09.0).

Thanks

David

Hi David,

Thanks for your support!

Do our customer have to set "DSI94 SOFT_RESET" while SOC leaves ULPS? 

There's a 3% failure rate with "soft_reset" while SOC leaves ULPS(system resume). 

There's almost 0 failure rate without "soft_reset" while SOC leaves ULPS. 

Do our customer need some actions for sn65dsi84 while SOC leaves ULPS? (seems to work well if we do nothing about the bridge.)

Many Thanks,

Jimmy

Jimmy

The SOFT_RESET bit must be set after making any changes to the DIS clock rate or after changing between DSI burst and non-burst modes. For when the SOC enters and leaves ULPS, are they changing the DSI clock? Can they probe the clock using a scope?

So if they remove setting of the SOFT_RESET bit, then the issue is resolved?

Thanks

David

Hi David,

We appreciated your great support!

The DSI (MIPI) paths are in the inner layer for good impedence and EMI so can't probe it. Is there any other way to check it? Please review the schematics as well again. Thanks a lot!

Jimmy