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SN65DSI84-Q1: Queries on TI DSI-LVDS bridge (SN65DSI84) boot sequence configuration.

Alan Xia
Genius 9600 points
Part Number: SN65DSI84-Q1
Other Parts Discussed in Thread: SN65DSI84,

Hi team，

We’ve few queries w.r.t recovery after link-loss detection (0xE5)

1. What recovery mechanism we’re going to implement for each error that’s corresponds to each bit in below registers.
2. With respect to correctable ECC and CRC error, is the bridge chip sn65dsi84 capable of handling it on its own without the intervention of software? (Chip level recovery).

  • 0
    TI__Mastermind 38200 points

    Hey Alan,

    I'm looking into this and will get back to you as soon as possible.

  • 0 in reply to Vishesh Pithadiya
    TI__Mastermind 38200 points

    CHA_SYNCH_ERR: This error is due to line time issue and can be resolved by ensuring that the DSI registers are set correctly using the the DSI tuner tool. On top of that please make sure that the line time measurements coming from the DSI source line up with that the register are set to.

    CHA_CRC_ERR: This is most likely due to issues in the communication channel itself. This can be due to a corrupted signal, bad cable connections, and improper setup of the bridge.

    CHA_UNC_ECC_ERR: This is due to a complete loss of what bits are correct and incorrect. This is a harder issue to narrow down the cause of because it  can be all f the above. 

    CHA_COR_ECC_ERR: This is due to some errors in the received data but within the threshold of error, so the ECC knows what bits are wrong. The SN65DSI84-Q1 does NOT handle these internally. This is usually handed by the sink. 

    CHA_LLP_ERR:  This is most likely caused by a line time issue, and can be resolved by ensuring the timing is correct

    CHA_SOT_BIT_ERR: This is also likely due to a line time error and can be resolved by fixing the line time.

    PLL_UNLOCK: This is due to the registers  DSI_CLK, DSI_CLK_DIVIDER, REFCLK, and REFCLK_MULTIPLIER. IF any of there do not match up with the DSI clock coming in and the LVDS clock for the panel this issue will trigger. 

    How to address these issues:

    1) toggle the PLL_EN

    2) double check that the DSI and LVDS data a nd clocks are configured & connected correctly

    3) restart the chip

    The SN65DSI84-Q1 does NOT handle the correctible errors internally, it only sets the flags.

  • 0 in reply to Vishesh Pithadiya
    TI__Genius 9600 points

    Hi Vishesh，

    Thanks for your help.

    The customer have further question：

    We want to confirm some more open points here.

    1、Do we have the only solution mentioned below for all error that occurred on register 0xE5?

    How to address these issues:

    1) toggle the PLL_EN

    2) double check that the DSI and LVDS data a nd clocks are configured & connected correctly

    3) restart the chip

    Or we can address each bit error separately ? If each bit error can be corrected, then please share info how we can achieve.

    2、From below bridge sn65dsi84 INIT sequence 2 & 8. How we can driver DSI clock lanes in HS and DSI data in LP11 from bridge driver code? If you have any reference document or patch, please share to us.

  • 0 in reply to Alan Xia
    TI__Mastermind 38200 points

    Driving the DSI lanes will be done using your video source. 

    the following E2E thread has a sample linux driver, but all software provided is as is and will not be supported or edited. 

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/549283/sn65dsi83-sn65dsi84-sn65dsi85---linux-driver/2006135#2006135

    The error bits are set when the SN65DSI84-Q1 see an error in the incoming or outgoing data. There is no one fix to resolve the issues as most issue on the device stem from incorrect data being passed into the device. 

    Here is a much more in depth debugging guide: https://www.ti.com/lit/an/slla356/slla356.pdf?ts=1701385143698&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FSN65DSI83

  • 0 in reply to Vishesh Pithadiya
    TI__Genius 9600 points

    Hi Vishesh，

    But the customer just need to confirm from your end the below mentioned is the only solution to recover all the error? If yes. They can proceed with given recovery solution.

    How to address these issues:

    1) toggle the PLL_EN

    2) double check that the DSI and LVDS data and clocks are configured & connected correctly

    3) restart the chip
  • 0 in reply to Alan Xia
    TI__Mastermind 38200 points

    Hey Alan,

    Its very difficult for me to say those are the only ways to fix the issue. These fixes will cover 99% of all problems, but I'm not confident saying fixing these will resolve all your issues. 

  • 0 in reply to Vishesh Pithadiya
    TI__Genius 9600 points

    Hi Vishesh，

    We’ve simulated the below 3 bits error of register 0xE5 and captured the observations:

     

    1. [BIT:0] PLL_UNLOCK: Observation: Display is getting blank.
    2. [BIT:1] Reserved.
    3. [BIT:2] CHA_SOT_BIT_ERR: masked, no effect on display.
    4. [BIT:3] CHA_LLP_ERR :  Observation: Display is getting blank.

     

    The detailed analysis, log & recovery mechanism has captured in attached docs linkloss_and_their_recovery.pdf

     

    The remaining below 4 bits we need to confirm from your end.

      1. How to simulate and what will be the impact on display?
      2. If its not taking effect on running display, can we mask and ignore these error bits?

     

    1. [BIT:4] CHA_COR_ECC_ERR:
    2. [BIT:5] CHA_UNC_ECC_ERR
    3. [BIT:6] CHA_CRC_ERR
    4. [BIT:7] CHA_SYNCH_ERR

     

    1. What is the de-bound time to get error settled down once init sequence performed on bridge? So, that we can avoid the false error on DSI bridge.linkloss_and_their_recovery.pdf
  • 0 in reply to Alan Xia
    TI__Mastermind 38200 points

    1. [BIT:4] CHA_COR_ECC_ERR:

         This bit is set when the SN65DSI84-Q1 detects a correctable ECC error. The SN65DSI84-Q1 does not have any error correction capabilities, so the effect on the display will be dependent on the display. To test this error you must insert errors in the DSI signal going into the device. You will find that there is a threshold of errors when a correctable ECC error will become uncorrectable. Some possible consequences of this error is a blank screen/ data corruption. To fix this error you must make sure the DSI signal going into the SN65DSI84-Q1 is a clean uncorrupted signal, and that the register settings line up with the DSI signal coming into the device. 

    2. [BIT:5] CHA_UNC_ECC_ERR

          Like mentioned in the correctable ECC error section this is the same error but at a higher frequency. The consequences, causes, and resolutions are all the same as the CHA_COR_ECC_ERR.

    3. [BIT:6] CHA_CRC_ERR

         This is a cyclical redundancy check error. This occurs when data transmitted is corrupted. In this sense this is very similar to the ECC errors discussed before. The causes of this are corruptions in the transmission of data. This is likely due to signal integrity issues and will be resolved when the data coming from the DSI lines is uncorrupted. Some consequences of this include screen flickering and screen going blank. 

    4. [BIT:7] CHA_SYNCH_ERR

         This is a vertical/ horizontal synch error in the video data. This is due to a mismatch in the register settings and the incoming DSI stream, additionally his can also be caused by corruption in the DSI lanes. This will cause the screen to be go blank. To address this issue ensure that the registers of the SN65DSI84-Q1 are set correctly, and the DSI stream is uncorrupted. 

    The error settle time is almost instantaneous. To double check that an error is not at falsely triggered reset the error bit register, and if it is re-toggled the error is a real error. 

    I would recommend operating where no errors are being seen by the SN65DSI84-Q1, but the correctable ECC error may be able to be masked without affecting performance depending on the display used. 

  • 0 in reply to Vishesh Pithadiya
    TI__Genius 9600 points

    Hi Vishesh,

    Thanks for the update and detailed explanation.

    Vishesh Pithadiya said:

    1. [BIT:4] CHA_COR_ECC_ERR:

         This bit is set when the SN65DSI84-Q1 detects a correctable ECC error. The SN65DSI84-Q1 does not have any error correction capabilities, so the effect on the display will be dependent on the display. To test this error you must insert errors in the DSI signal going into the device. You will find that there is a threshold of errors when a correctable ECC error will become uncorrectable. Some possible consequences of this error is a blank screen/ data corruption. To fix this error you must make sure the DSI signal going into the SN65DSI84-Q1 is a clean uncorrupted signal, and that the register settings line up with the DSI signal coming into the device. 

    • As, per the above comments. DSI signal coming to bridge sn65dsi84 should be clean and un-corrupted. So, please correct me if I’m wrong.
      • We can’t correct it from bridge driver as mentioned (SN65DSI84-Q1 does not have any error correction capabilities).
    • As per the comments “correctable ECC error may be able to be masked without affecting performance”.
      • So, we can mask this bit error.
    • Is this flicker issue being momentarily and will get corrected in next correct frame?
      Vishesh Pithadiya said:

      2. [BIT:5] CHA_UNC_ECC_ERR

            Like mentioned in the correctable ECC error section this is the same error but at a higher frequency. The consequences, causes, and resolutions are all the same as the CHA_COR_ECC_ERR.

      > same as mentioned above.

      Vishesh Pithadiya said:

      3. [BIT:6] CHA_CRC_ERR

           This is a cyclical redundancy check error. This occurs when data transmitted is corrupted. In this sense this is very similar to the ECC errors discussed before. The causes of this are corruptions in the transmission of data. This is likely due to signal integrity issues and will be resolved when the data coming from the DSI lines is uncorrupted. Some consequences of this include screen flickering and screen going blank. 

      > This flicker issue being momentarily and will get corrected in next correct frame as per the above comment (will be resolved when the data coming from the DSI lines is uncorrupted)

      > So, we can mask this bit error.

  • 0 in reply to Alan Xia
    TI__Mastermind 38200 points

    The flickering/ blank screen will depend on how your video panel handles the corruptions, so I cannot say what the effects will be be for your application. I can only speak on what some common issues are. You are correct in that the SN65DSI84-Q1 has no built in error correction so it will be dependent on the DSI source or LVDS sink to handle these issues.

    The flicker issue typically doesn't go away in the next frame and I would highly recommend NOT masking any of the error bits.