SN65DSI84: SN65DSI84 Single DSI to dual LVDS

Felix Radensky50

Part Number: SN65DSI84

Hello,

I have trouble following this guide https://training.ti.com/sites/default/files/docs/singletodual_0.pdf to calculate LVDS and DSI clocks. The panel resolution 1920x1080, the connection is single DSI to dual LVDS.

Panel clock is 141.2MHz, refresh rate is 60Hz, 24bpp, 4 lanes. Following the formula on page 5 I get

DSICLK = (2 x 141.2 x 24) / (2 x 4) = 847.2 MHz, which is larger than maximum DSI clock frequency of 500MHz. What am I missing ?

Thanks a lot.

over 5 years ago

0 Ikechukwu Anyiam over 5 years ago

TI__Mastermind 35130 points

Felix,

If your operating mode is single DSI to dual LVDS, then you panel probably has 2 LVDS clocks, so the LVDS CLK frequency is 70.6 MHz (141.2÷2). You should check your panel datasheet to verify. Your equation should come out to be:

DSICLK = (2 x 70.6 x 24) / (2 x 4) = 423.6 MHz

Regards,

I.K.

0 Felix Radensky50 over 5 years ago in reply to Ikechukwu Anyiam

Prodigy 140 points

Hi,

Thanks for a prompt reply. The panel datasheet can be found here: https://www.fortecag.de/fileadmin/user_data/Dokumente/Datenblaetter/Displays/TFT_Displays/13.3/G133HAN01.0_Datasheet.pdf

Your answer makes sense. What do you think should be done with HFP, HBP and HPW parameters from datasheet ? Should I use half the datasheet value in Panel Inputs tab and actual datasheet value in DSI Inputs tab ?

Thanks.

0 Ikechukwu Anyiam over 5 years ago in reply to Felix Radensky50

TI__Mastermind 35130 points

Hi Felix,

Yes that should be correct. It's strange that the panel datasheet does not indicate the horizontal parameters should be divided by 2. Most dual LVDS panel datasheets I've seen show the horizontal parameters already halved in the timing table.

Regards,

I.K.

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SN65DSI84: SN65DSI84 Single DSI to dual LVDS