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TSB81BA3E: TSB82AA2B+TSB81BA3E questions

Kailyn Chen
Genius 9560 points
Part Number: TSB81BA3E
Other Parts Discussed in Thread: TSB82AA2B,

Hello，

One customer used  two TSB82AA2B+TSB81BA3E to realize 1394 transmission and receive. 

About the AT questions,

1. Except to use the interrupt registers, is there any other method to confirm data has been transmitted to the other ended? And what is the sequence( which register to check first, and then what registers to  check again)

About the AR questions, 

1. after write to  AR DMA Context Programs  .INPUT_MORE descriptor, the feedback data is almost the data which is written to INPUT_MORE descriptor, and didn't receive any transmitted data.

2. Do you have reference design?

Best regards

Kailyn 

  • 0
    Guru 267180 points

    1. The only alternative for the *TxComplete interrupts would be to poll the xferStatus field in the OUTPT_LAST(_Immediate) descriptor. If your architecture does not have DMA-coherent memory, this might be more involved than interrupts.

    2. When receiving data, only the xferStatus and resCount fields in the INPUT_MORE descriptors are updated. When resCount is written, the related packet data is guaranteed to have been written to the data buffer. This question does not have enough information to determine what might be wrong with the descriptors; show the descriptors.

    3. The TSB82AA2B conforms to the OHCI specification. You can use any OHCI host controller implementation. Open-source implementations can be found at git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firewire/ohci.c and cgit.freebsd.org/src/tree/sys/dev/firewire/fwohci.c.

  • 0 in reply to Clemens Ladisch
    TI__Genius 9560 points

    Hi Clemens,

    Thank you for your reply.

    When the first transmit data, receive xferStatus=16'h8451,eventcode feedback ack_complete； IntEvent.reqTxComplete=1'b1。

    Clear IntEvent.reqTxComplete, and the second time to start DMA context, but there is no response of 1394OHCI, and didn't read DMA descriptor, what is the reason? Does it wait response or confirmation packet? Must a request  transaction correspond to a response  transaction? Continue to launch DMA context and still not responding.

    When the first receive data, IntEvent.busReset is driven, after clear IntEvent.busReset, lauch DMA context, AR_Req_CCPtr

     fill in  X"7FF0_0081",

    The descriptor is as following:

    Address 0X7FF0_0080 :   X"283C_0094" ，

    0X7FF0_0084:             X"7FF0_1000",

    0X7FF0_0088:   X"0000_0000",

    0X7FF0_008C:   X"0000_0094",

    Recieve data ：address 0X7FF0_1000:  X"283C0094"，

    0X7FF0_1004:   X"28000094"，

    0X7FF0_1008:    X"28000094"，

    0X7FF0_100C:   X"28080094"，

    0X7FF0_008C:   X"283C0094"，

    eventcode feedback evt_bus_reset, but couldn't receive Bus Reset Packet or  Block write request receive format, why?

    Best regards

    Kailyn