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DS90UB941AS-Q1: External reference clock mode

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: CDCEL937-Q1, CDCE913-Q1, CDCE6214-Q1, , DS90UH941AS-Q1, CDCM6208

Hi,

If we use the External reference clock mode of DS90UB941AS, what's the recommended IC to provide the clear reference clock for 941? As you know the jitter requirement is 0.28UI max.

  • Hi Ying,

    The 941AS EVM uses LMK61E0M, which operates up to 200MHz.

    For Automotive grade, depending on your application configuration, you could also look into the following parts: CDCE913-Q1CDCEL937-Q1CDCE6214-Q1

    Regards,

    Fadi A.

  • Thanks for your reply. I see that different parts have different jitter spec. And the jitter requirement of 941 varies depending on different pixel clock frequency.

    If the pixel clock is 62MHz for single FPD-Link, which part is suitable?

    If the pixel clock is 210MHz for dual FPD-Link, which part is suitable?

    There is cycle-to-cycle jitter and period jitter in the datasheet of CDCE913-Q1 and CDCEL937-Q1, which type of jitter should be evaluated?

    Thanks in advance, and look forward to your reply.

  • Hi Ying,

    for the jitter requirements for 941AS please refer to the following link. It goes over it in full details. 

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1050269/faq-ds90ub941as-q1-dsi-or-refclk-jitter-measurement?tisearch=e2e-sitesearch&keymatch=ds90u%2A

    Regards,

    Fadi A.

  • Hi,

    I have read it and understood the jitter requirement of 941AS, but I still not understand whether the ouptut jitter spec of CDCE913-Q1, CDCEL937-Q1, CDCE6214-Q1 can meet the jitter reqirement of 941AS. Because they mention different jitter type like period jitter and cycle to cycle jitter instead of Tj.

    So could you tell me 

    If the pixel clock is 62MHz for single FPD-Link, which part can meet the jitter requirement of 941AS?

    If the pixel clock is 210MHz for dual FPD-Link, which part can meet the jitter requirement of 941AS?

    Regards,

  • Hi Ying,

    Target total input jitter specification per the 941AS Reference clock jitter spec in the datasheet is 0.28 UI, so in your case, the calculations would be as follows:

    Dual lane - (1/(35*210/2))*0.28 = 76 ps 

    Single Lane - (1/(35*62))*0.28 = 129 ps

    The input jitter for 941AS is specified across a specific frequency band which is related to the 941AS PLL characteristics so it does not directly compare to the specifications for the listed CDCEx9x datasheet jitter parameters. 

    Given that the DS90UB941AS-Q1/DS90UH941AS-Q1 jitter requirements are for Total Jitter. In order to characterize total jitter, TI recommends to measure the TJ@BER with a high speed oscilloscope equipped with a jitter analysis program such as DPOJET.

    The clock recovery settings used in the DPOJET measurement are designed to match the input PLL characteristic of the 941AS serializer device:

    • Method = PLL Custom BW
    • PLL Type = Type II
    • Loop BW = f/40 for dual FPD-Link (where f = PCLK)
    • Loop BW = f/20 for single FPD-Link (where f = PCLK)
    • Damping = 2
    • Target BER = 1e-10
    • High pass filter: None
    • Low pass filter: First order, f/20 for dual FPD-Link (where f = PCLK)
    • Low pass filter: First order, f/10 for single FPD-Link (where f = PCLK)

    You would need to measure the CDCEx9x REFCLK output jitter using the above settings to ensure that it meets the total input jitter spec for 941AS. Please refer to the following link: https://www.ti.com/lit/pdf/SCAA120B  on more detail about how to measure total jitter (TJ@BER). This link is an application report that describes the recommended measurement techniques for TJ. It includes the description of the techniques to minimize the noise sources of the measurement equipment. The CDCM6208 characterization setup is used as an example throughout the application report.

    Regards,

    Fadi A.