SN65DSI83-Q1: Timing variation of LVDS output

Hello Harry,

What did you all measure for line time for the LVDS output? Please provide oscope snapshot. I only see line time calculation for the DSI input.

Also, the DSI Tuner tool allows you to calculate the line time. Could you click on the calculator icon to see what the tool expects for your line time?

Thanks,

Zach

Hello Zack,

OK. I will provide it. for DSI, there was guidance in E2E as below.

[FAQ] SN65DSI84: How to debug flickering video with SN65DSI83, SN65DSI84, and SN65DSI85 - Interface forum - Interface - TI E2E support forums

but no information for OLDI measurement method.

could you pls provide example for it?

Thank you.

Hello Harry,

Unfortunately, we don't have OLDI measurement method example. In the DSI Tuner tool, there is a Calculator icon you can click on to make sure the DSI and LVDS clocks closely match when configuring the device.

I will look into the parameters that you measured and their implications.

Thanks,

Zach

Hi Harry

Also what is the DSI clock frequency they are using? Do they have the ability to switch from DSI CLK to Reference Clock as the clock source and see if the issue still shows up? 

For the scope measurement, did they measure it when the issue happens? 

Thanks

David

Hi, 

Below is the reply from the field

1. 1. There are two questions on the LVDSCLK that needs to be answered by vendor

1. LVDSCLK calculated from HtotalxVtotalxFrame rate does not 100% match with the LVDSCLK frequency listed in the panel vendor, which LVDSCLK frequency we need to use for the line time calculation?
2. What is the min and max LVDSCLK frequency as it is not listed in the panel datasheet. Typically the panel tolerate certain amount of LVDSCLK offset

                                --> LGE: Display Tier 1 company provided only typical value(61MHz)

1. 1. Is the issue being reported with one particular panel or across multiple panels?    

                                               --> LGE : Multiple panels

1. Too much jitter on DSI CLK. Can they switch to reference clock as the clock source as reference clock jitter is less than the DSI CLK? LG indicated they can’t do that. In this case, do they have a way to reduce the DSI CLK jitter?

                                                --> LGE : refer to attached D-PHY CTS Test report with no issue (page 3)

1. When they did the A-B-A swap, did they test against the same panel?

                                  --> Yes

MIB3_OI_LGE_ABT image vibrates_for ti_20221005 (002).pptx

Thanks

David

Harry

The scope shot in the attached presentation, are they taken with a good unit or the bad unit?

Thanks

David

Hello David,

Those scope shot is from bad unit. but it is very hard to reproduce issue with issue sample in LG hand. because they have sent one high failure rate issue sample. As LG reported, each sample has different failure rate. (1~2/10times power on/off test from issue sample in your hand, but other issue sample only has 1~2 times failure rate per 500~1000times or more on/off test).

LG have tested as below item by themselves. FYI.

1) change 0x29 to adjust Sync delay ==> has issue. (issue means H front porch/H back porch has variation)

2) change PCLK ==> has issue (issue means H front porch/H back porch has variation)

3) change H blanking parameter  ==> has issue (issue means H front porch/H back porch has variation)

I guess you are focusing on line time mismatching between OLDI and DSI.  I think it would bring fifo error if line mis-matching issue happen. is there error flag to see this??

Thank you.

Hi, Harry

I guess you are focusing on line time mismatching between OLDI and DSI.  I think it would bring fifo error if line mis-matching issue happen. is there error flag to see this??

My focus is still on the line time mismatching between the input and the output. The video transfer is done on a line-by-line basis in the SN65DSI83. The size of the buffer in DSI83 is only one video line, so it is important to match the line time (Sync-to-Sync time) between the input and the output. It is also important to maintain the data rate so as not to underflow or overflow the internal buffer. 

On the DSI input side, the data is clocked in with the DSI_CLK. The DSI_CLK also drives the OLDI clock. Previously, LG reported that Issue doesn't happen when change LVDS CLK RANGE value (address 0x0a) from 0x03 to 0x01 for 1000 times cycle test on 2ea issue samples, is this still true?

Again, this makes me question LG clock calculation and whether it is correctly meeting the panel vendor clock requirement.

Thanks

David

Hello David,

- For your 1st quesiton, Yes, one issue sample LG sent to QA has such a behavior. this issue sample has highest failure rate. if change LVDS CLK range from 001 to 000, issue is resolved.  but they configure same setting to other device, some of device has failed to display.

- For your 2nd question, I think so, panel vendor doesn't concern OLDI CLK. they challenged LG that device output has 2pixel of H front/back porch timing variation.

- For Line time measurement, let me do onsite to measure accurate result for line time both OLDI and DSI.

BTW, I think there would be measurement tolerance between them and clock jitter as well. what is your acceptable tolerance for line length between them?

- Last question is that OLDI line is made by device there is no option to adjust it. I understand even I change DSI input a little, OLDI line time also could be changed a little accordingly. Is there any misunderstanding??

Thank you.

Hi, Harry

- For your 2nd question, I think so, panel vendor doesn't concern OLDI CLK. they challenged LG that device output has 2pixel of H front/back porch timing variation.

Again, line time on DSI input and LVDS output MUST match while there is no need to match the horizontal sync or porch parameters. So even though there is horizontal back/front porch variation, the Htotal is still the same.

BTW, I think there would be measurement tolerance between them and clock jitter as well. what is your acceptable tolerance for line length between them?

This depends on the panel and goes back to my question, how much frequency variation can the panel tolerate?

- Last question is that OLDI line is made by device there is no option to adjust it. I understand even I change DSI input a little, OLDI line time also could be changed a little accordingly. Is there any misunderstanding??

The line time depends on the DSI input, the DSI83 does not change the line time.

By the way, do they have a way to measure the VSYNC and make sure it is meeting the panel 59.7MHz requirement?

Thanks

David

Hello David,

David (ASIC) Liu said:

The line time depends on the DSI input, the DSI83 does not change the line time.

By the way, do they have a way to measure the VSYNC and make sure it is meeting the panel 59.7MHz requirement?

=> DSI83 doesn't change line time. but now you are focusing on line time. so I am curious why you suspect line time.

I think it should be matched because DSI83 device doesn't change it if register configuration is correct.

Can you help me understand about your concern?? if you let me know your guess for issue mechanism, it would be helpful to understand.

for your request of Vsync, Do you mean you want to check Vsync frequency (frame rate)??

if so, we can check it from Vsync data in OLDI line (olid 2nd pair) or LP11. I will get back to you.

You can let me know measurement data which you want to check. (I cannot visit frequently LG to test)

then I will arrange my onsite schedule tomorrow.

Thank you.

Hi, Harry

My response was to your question "Last question is that OLDI line is made by device there is no option to adjust it. I understand even I change DSI input a little, OLDI line time also could be changed a little accordingly. Is there any misunderstanding??". The line time is determined by the DSI input. But flicking issue can have when the line time on the LVDS output does not match with the line time on the DSI input. 

for your request of Vsync, Do you mean you want to check Vsync frequency (frame rate)?? -> Yes, please check VSYNC when there is an error condition.

Can you also put the scope in persistent mode when measuring DSI CLK and LVDS CLK, are you seeing any shift in the DSI CLK or LVDS CLK with the bad units?

Thanks

David

Hello David,

I will measure DSI CLK and LVDS CLK and will get back to you. and will try to capture power on sequence clearly with I2C signal.

and will provide Vsync and line time measurement for your information.

David (ASIC) Liu said:

But flicking issue can have when the line time on the LVDS output does not match with the line time on the DSI input. 

==> Yes, if assume LVDS line time is not mismatched with DSI, how we can resolve it??  Do you think device cause issue if line time mismatching happen?? 

I cannot imagine how SOC can cause line mismatching between DSI and OLDI.

Thank you.

Hi, Harry

If there is a line mismatch, the DSI source has to correct it. The DSI83 does not have the ability to correct the line time. 

If you look at the Troubleshooting SN65DSI8x - Tips and Tricks App note, https://www.ti.com/lit/an/slla356/slla356.pdf, the DSI8x does not realign timing, so if the line time is different then there will be issues.

Thanks

David

Hello David,

pls refer to attached for your request.

I added line time. and both line time are measured in same scope window.

I believe they have same line time.( pls note it could have measurement tolerance with several nano seconds.)

pls refer to page #5~7

MIB3_OI_LGE_ABT image vibrates_for ti_20221014.pptx

Thank you.

Harry

Are these waveforms captured during the failure? The VSYNC, DSI CLK and the LVDS CLK frequency all look correct from the waveform.

Is it possible that you can send me the platform to me for debugging?

Thanks

David

Hello David,

Yes, I agreed I also couldn't find any abnormal behavior on system side.

Unfortunately, I have no way to trigger issue case. but because issue follows sample, so I understand that it would not be depend on specific system behavior.

Let me ask LG to send system to you. I will get back to you.

Thank you.

Harry

We need to capture the waveform during the issue case. But so far I am not seeing issues with the captured waveform.

Thanks

David

Hello David,

Sorry for late reply.

LG is preparing to send system to you.

Can you inform your address I send to??

Thank you.

Harry

I sent you my mailing address in an email.

Thanks

David

Hello David,

CQE team will send system soon.

Do you have any equipment like DSI analyzer??

LG is wondering what item you will verify.

Can you help answer your plan for system verification when you receive it??

Thank you.

Harry

I do not have a DSI analzyer. Mainly I want to see if using a reference clock instead the DSI CLK, whether the issue is still repeatable or not.

Thanks

David 

Hello David,

Our CQE team sent system to you.

Do you have any idea to change clock source in customer board??

Thank you.

Harry

The plan is to use an external reference clock to manually input the clock into DSI83-Q1.

Thanks

David

Hello David,

DSI83-Q1 device on system I sent you has very low failure rate. 1time issue happen per several thousand trials.

So I recommend you test this with sample LG sent before for ATE test.

Here is information of system.

LG Board test connection for SN65DSI83.pptx

Thank you.

I had call with customer. Can you provide 1st verification result in Monday in your time?  FYI, they evaluated 5 units with hundreds on/off test. and confirmed same issue observed, intermittently.  Car OEM is taking it seriously as ramp up is coming. every wed in Europe time set a regular call

Hi,

Since we have not received the board and it will take time to swap in the unit, set it up, and then try to duplicate the issue, have some result by Monday will not be possible. But we will do our best to have some result by Wednesday depending on when we will receive the board.

Thanks

David

Hello David,

Let me post your question on here.

Hello LG team

Could you pls answer those question as below??

• The connector that connects to the display is not key’ed, which orientation is the right way to plug the connector into the display?
• There is a yellow and a purple color connector on the main DSI83-Q1 board, can you please confirm the display cable needs to be plugged into the purple connector?
• Visual inspection shows there are damaged component on the main DSI83-Q1 board (see below picture), please confirm if they need to be fixed first.

Thank you

Dear. Sir,

Please refer to below picture.
I've already shared it by email, but I'm sharing it again.

1. The display cable direction is the same as the picture below.

2. Connect the quadlock cable to the PCB.

3. Display cable connection

4. After connecting the display, connect the power supply to the part indicated below on the Quadlock cable and apply 14V.

And, Damaged parts are related to Ethernet function, so there is no problem in display test.
So, I look forward to your reply as soon as possible.

Thanks.
Best regards, Kumin

Kumin

Thanks for the setup instruction. Following the setup instruction and powering the board with 14V, I still do not see display lights up. 

I did however checked DSI83-Q1 power up sequence, below is the screen shot.

Channel 1 - VCC

Channel 2 - DSI_CLK

Channel 3 - EN

What I noticed is the DSI_CLK is not in HS CLK mode. Is it possible to configure the DSI source so the clock is in HS CLK mode? This is part of the DSI83-Q1 power up sequence requirement.

Thanks
David

Dear. David

Could you send set-up instruction picture first?
(Just want to check your set-up correctly or not.)

For example.. As below picture.

1. PCB Board

2. Display

3. Quadlock cable

4. Display connection & 14V power


And, Could you explain detail below comment?
You mean need to revise Software for HS CLK mode?
"What I noticed is the DSI_CLK is not in HS CLK mode. Is it possible to configure the DSI source so the clock is in HS CLK mode? This is part of the DSI83-Q1 power up sequence requirement."

Thanks.
Best regards, Kumin.

Kumin

I will provide the setup picture tomorrow. 

For HS CLK mode, please refer to this scope plot. You want to make sure the DSI CLK is already running in the DSI High Speed mode when EN pin goes from low to high.

Thanks

David

Dear. David

Thank you for your reply.
I heard LGE SW engineer already revised power sequence as you mentioned, but Issue was occured.

And, I checked yesterday, When the issue was occured, V_active_width, V_Period was shaking mainly. (H_porch is also unstable)
Please refer to attached picture.


So, I will check Scope cauptre one more when the issue is occured soon.

I'm also reviewing it, So Please check this issue as well.
I look forward to your reply.

Thanks.
Best regards, Kumin.

Kumin

Please see below for the connection picture.

Could you please ask LGE SW engineer to double check the DSI83-Q1 power-up sequence? We need to make sure the correct power-up sequence is being followed.

Thanks

David

Hello Koomin,

if VT is abnormal, another legacy  panel which have used before also show issue. but as far as I know, legacy display module doesn't have it.

I understand issue only happen new panel.

Am I correct?? 

Thank you

Dear. David

I plan to check the power sequence by measuring it with an oscilloscope today.
And, In the picture below, the cables are connected in reverse.

I have a question as below.

If you look at the waveform below, when booting, LVDS_CLK initially oscillates at about 3 MHz for 1.7 seconds and then oscillates at 62 MHz.
It isn't not LGE SW setting.
Is it normal to oscillate at 3 MHz?

Thanks.
Best regards, Kumin.

Kumin

I am now able to get the display working with the change in the cable orientation. 

For your scope capture, can you also probe the DSI83-Q1 EN pin and see when it is toggling from low to high along with the DSI_CLK and LVDS CLK?

Thanks

David

Dear. David

Could you send set-up instruction pictures as below one more ?
1. Display


2. PCB Board
Just want to check below point


And, LGE SW engineer revised power-up sequence as below but issue was also occured.
Is it right power-up sequence?
(SW revise : CSR init performed in the LP-11 state section.)

Thanks.
Best regards, Kumin.

Kumin

The revised power-up sequence looks correct. With this sequence, are you seeing the correct LVDS output clock?

Can you share the step to update the board in my lab so I can continue to look at this issue with the revised sequence? 

Also, is there a way to read/write DSI83-Q1 register? I tried to use an external I2C controller to read/write DSI83-Q1 and can't do it.

Thanks

David

Dear.David

Your PCB Board is also as same as mine.
So, I think you can check the power sequence on your board.
Now I think you have to check on your side as to why the issue is occurring.

"Also, is there a way to read/write DSI83-Q1 register? I tried to use an external I2C controller to read/write DSI83-Q1 and can't do it."

 -> If you have environment to use shell command by connected uart line, you can easily use shell command to read/write registere of bridge ic.
     But you can't use in your environment.
     I think please let us know the register you want to read / write.
     and We will excute as you want and get back to you.

Thanks.
Best regards, Kumin.

Kumin

In your response, you said "And, LGE SW engineer revised power-up sequence as below but issue was also occurred.", how do I revise my power-up sequence? 

Once the SOC has programed DSI83-Q1 register, can it release the I2C bus so I can use an external I2C controller to control the DSI83 register? 

Thanks

David

Dear. David

I mean your PCB Board already has updated SW with modified power sequence.
So, If you check power sequence, maybe you can see correct power sequence on your PCB Board.

It's urgent, Please quickly analyze the cause of the issue.

Hello David,

I have discussed with Kumin and request/question as below.

Could you pls kindly support those items??

1) Have you reproduced issue with LG board??

2) For power up sequence, your board power up behavior is same as board which Koomin has.

  but you can find same power up sequence as what Koomin showed at 2nd "EN" signal toggle.

  Can you zoom out more to confirm power up sequence at your board?? then you can find correct power on sequence.

3) I understand you want to access device via I2C for further test.

While LG find a way for you to access device via I2C, LG and I want to do test which you want to try.

Could you pls list up your test items for LG and I can do??

4) I was told that you want to test ref clock mode. LG is finding ways how to they can implement external clock mode.

Thank you.

Harry

I am able to duplicate the issue in the lab, let me see if I can capture the 2nd 'EN' signal toggle to verify the power sequence.

Thanks

David

Hello David,

Good to know it.

And can you tell me what item you want to try to test??

While LG find away how you can access device via I2C, LG also want to join verify issue with us.

pls share your verification idea with I and LG.

1more quick question is,

I remembered you want to try to use REFCLK mode.

so I understand that REFCLK by OSC should be same as 61MHz OLDI CLK. Am I right??

Thank you.

Harry

My focus is to try the external reference clock, but it does require I2C access to change the DSI83 input clock selection. 

If an external reference clock is selected, it is multiplied by the factor in REFCLK_MULTIPLIER (CSR 0×0B.1:0) to generate the LVDS output clock. By default, LVDS clock is the same as the reference clock.

Thanks

David

Dear David

Regarding the I2C access.

I guess I2C to SoC need be disconnected by removing R4062/4061 on below 

Hi,

Thanks, I requested to replace the two resistors with jumper. The jumper will be populated so the DSI83-Q1 can be programmed first upon power up. Once it is powered up, then I will use the jumper to switch to the external I2C controller. 

One question, does the panel get powered up before the DSI83-Q1 provide a valid LVDS CLK to it or do you wait until the DSI83-Q1 has a valid LVDS CLK?

Thanks

David

I am not sure because Display is made by another company but Panel might be power up after LVDS output like [ LVDS -> FPD link lock --> Display panel power up ]