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DS90UB948-Q1: i2c SCL configuration

Part Number: DS90UB948-Q1

hi team,

Can you share some materials on the I2C SCL setting of deserializer? Customer found the SCL setting is not aligned with register setting, 948: 0x26=0x17; 0x27=0x17 (should be 400kHz but the test results is 250kHz)

948 I2C waveforms: SCL=250kHz

949 I2C waveforms

Regards,

Dongbao

  • HI Dongbao,

    I will have to look into this and get back to you. In the meantime here are two I2C appnotes that apply to FPD3 devices.

    6318.snla131a.pdf

    6840.snla222.pdf

    Regards,

    Ben

  •  Hi Ben,

    Do you have any update?

    Dongbao

  • Hi Dongbao,

    Is the 948 the controller in this case? The way to set the I2C rate is by programming the HIGH/LOW time as you pointed out. However, this only works when the 948 is acting as the controller. Otherwise, the I2C rate is set by whatever rate the controller is transmitting.

    Regards,

    Ben

  • hi Ben,

    It's i2c pass through application, 948 definitely work as proxy master, pls help check whether the calculation works for 948

    For 400kbits remote i2c rate, the scl high&low should be 0x17 instead of 0x32. 

    For 0x32, scl high time=scl low time=50*50ns=2.5us, scl period is 5us thus the data rate is 200kbit/s.

    Could you validate the customer's findings in the bench?

    Dongbao

  • Hi Dongbao,

    This table has setting specifically for the 913/914, so the actual register programming might not match all FPD-Link III devices. Can you clarify what communication is actually taking place here? Is the command coming from the 949, passing through he 948 to a remote device, or is it directly to the 948? Maybe a block diagram would be helpful.

    Also, what high/low time is programmed into the 949?

    Regards,

    Ben