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DS90UB962-Q1: SerDes Register Settings & Clarification

Mayunthan Nithiyanantham
Intellectual 785 points
Part Number: DS90UB962-Q1

Hi Team, 

Cc:  

I have a few questions on the ub962 Register settings. Could you please clarify the below items? 

  1. Register 0x19, 0x1A, 0x1B, 0x1C (FS_HIGH_TIME & FS_LOW_TIME)
    • Currently our configuration for both Fisker and CVADAS, is to use Externally Generated FrameSync.  As such, we believe we don’t need to configure these registers and we can leave them as Default (0x00).  Could you please confirm?
  2. Register 0x1D (MAX_FRM_HI) and 0x1E (MAX_FRM_LO) – Maximum frame counts: Do we need this configured? What is the difference between HI and LO registers here?
  3. Register 0x21 (FWD_CTL2) = 0x03 : Do we keep this as Default? With the Default configuration, the Video traffic will not be synchronized, data forwarded based on Round Robin fashion. Synchronized forwarding disabled.
    1. Should we enable Synchronized CSI-2 forwarding for the Surround View Cameras? Ahat is the importance of this Register? I am under the impression that this offers synchronization of all incoming data.
    2. If we're to enable this, which of the following should I choose from? Please clarify the differences:
      • 01: Basic Synchronized forwarding enabled
      • 10: Synchronous forwarding with line interleaving
      • 11: Synchronous forwarding with line concatenation
  4. Register 0x32 (CSI_PORT_SEL)
    • Our current configuration for both Fisker and CVADAS is at 0x01 (where we enable TX_WRITE_PORT Bit 0 to 1).  Is this configuration sufficient?
    • Our i2c dump for Fisker shows 0x03, which means Bit 1 is 1, but in the datasheet Bit 1 shows as RESERVED. Could you please clarify on this?
  5. Register 0x36 (CSI_TX_ICR)
    • We currently have this register with the Default value of 0x00.
    • At Value 0 – is it enabled or disabled for these error interrupts?
    • Can we keep these settings as Default?
  6.  0x41: SFILTER_CFG Register We have currently configured it as 0xA9 (which is the Default). Is this correct for AEQ adaption? Will this remain the same for Asynchronous mode as well?
  7. 0x42: AEQ_CTL Register – currently we’re using the default value of 0x71.  Could you please provide us more information on this Register? What is the difference between AEQ/SFILTER inner and outer loop in Bit 1? What is the best choice for Bits 1 & 2 in this register? What do you recommend?
  8. 0x4A: FPD3_CAP: We have two enums for bit 4 of this register.
    • FPD3_ENC_CRC_CA 
      • 0: Disable CRC error flag from FPD-Link III encoder
      • 1: Disable CRC error flag from FPD-Link III encoder (recommended)
      • Could you please help us understand the differences between the two?
  9.  0x46: BCC_ERR_CTL Register: We’re using the Default value 0x20 where we only have the “Enhanced Error Checking” enabled.  Is this fine? Do you recommend another additional bit to be set here?
  10. 0x6D: PORT_CONFIG Register : Our current value is set at 7C.  The Deserializer will be connected to ub953 Serializer in the Camera. Since ub935 is very similar to ub953,  I just want to confirm that the values we see as 00 for Bits 1:0 is correct for FPD3_MODE.
  11. Because we are using externally generated framesync, the only Registers to configure here are 0x18, 0x6E, and 0x6F, correct?
  12. Register 0x18 needs to be configured for external signal to be passed (through one of the GPIO pins), which we have done.
  13. Registers 0x6E, 0x6F – do we need these configured in order to send the framesync signal via GPIO to the Serializers? Can the framesync signal be sent via i2c back channel alone?

Thank you!

  • 0
    TI__Genius 14175 points

    Hi,

    Thanks for reaching out on these questions. Included some feedback here below:

    1. Frame sync registers:
      1. [Thomas]: Correct, these registers are specific to internally generated frame sync, no need to configure for externally generated frame sync
    2. Register 0x1D (MAX_FRM_HI) and 0x1E (MAX_FRM_LO)
      1. [Thomas]: These registers may not need to be configured depending on expectation from SOC. The max frame count register is 16 bit with the hi and lo being split into two separate registers
    3. Register 0x21 (FWD_CTL2)
      1. [Thomas]: The default configuration of this register is 0x03 if noted. Generally the sync mode is left up to the discretion of system designers. If there is no need for video synchronization and the system was not designed with this in mind best effort round robin is likely the best option here.
    4. Register 0x32 (CSI_PORT_SEL)
      1. [Thomas]: The DS90UB962 has only one CSI TX port, no need to change this register setting. Please avoid writing 0x32[1] to 1 rather than the default value of 0.
    5. Register 0x36 (CSI_TX_ICR)
      1. [Thomas]: Okay to keep this register as default, interrupt usage is based on system requirements 
    6. 0x41: SFILTER_CFG Register
      1. [Thomas]: Recommended to leave this register as default (0xA9)
    7. 0x42: AEQ_CTL Register
      1. [Thomas]: Under normal circumstances we generally would not recommend making any changes to the AEQ settings. Page 5 of the margin analysis program application note has a helpful diagram to understand AEQ.
    8. 0x4A: FPD3_CAP
      1. [Thomas]: The recommended option has a typo, this should state enable CRC error flag for FPD-Link III encoder which is recommended. Please set this bit to 1
    9. 0x46: BCC_ERR_CTL Register
      1. [Thomas]: Default configuration should work okay here
    10. 0x6D: PORT_CONFIG Register
      1. [Thomas]: Setting this register to 0x7C should work okay here. CSI-2 mode on the 935 should work with no issue as this is a CSI-2 serializer. 
    11. External Frame-sync
      1. [Thomas]: 0x18: setup for externally generated frame sync on specific GPIO. 0x6E/0x6F: Configure pass through to a specific GPIO pin on the serializer.  Details on how to operate this are contained in section 7.4.24.1 of the DS90UB962 datasheet. 
    12. GPIO pass through configured for external frame sync, sounds good.
    13. 0x6E & 0x6F: BC_GPIO_CTL0 & BC_GPIO_CTL1
      1. [Thomas]: GPIO pass through is packaged into the back channel frame along with I2C. These registers should be set to select which GPIO on the ser side the frame sync signal is routed to. 

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    Intellectual 380 points

    Hi Thomas,

    Thanks for your inputs.

    I had a few more queries.

    1) For Register 0x36 (CSI_TX_ICR) can I know if 0 value represents if we are enabling/disabling the interrupt?

  • 0 in reply to Rutuja Kate
    Intellectual 380 points

    2) For register 0x1F (CSI_PLL_CTL Register): Bit 1:0 is CSI-2 Transmitter Speed select. I need your help to understand what value I should configure here.

    We are using the below configurations:

    ECU = 962 non-synchronous mode (Mode 0)

    Camera = 953 non-synchronous mode internal AON clock (Mode 3)

    The back-channel frequency 10Mbps.

    We are utilizing maximum of approx 1.1 Gbps CSI bandwidth and our external clock for the deserializer is 25MHz.

  • 0 in reply to Rutuja Kate
    TI__Genius 14175 points

    Hi Ratuja,

    Thanks for the follow up. Included feedback on this below:

    1. 0x36: CSI_TX_ICR
      1. [Thomas]: Please see section 7.5.9 of the 962 datasheet for interrupt support. Register 0x36 controls the interrupt for the CSI-2 TX port. It could be helpful to look at registers 0x23 and 0x24 for the different interrupts which can be triggered.
    2. 0x1F: CSI_PLL_CTL
      1. [Thomas]: Section 7.4.19 has details on CSI-2 Tx frequency. Do you have the details of the imagers which will be used in this application? 

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    Intellectual 380 points

    Hi Thomas,

    The imager used is Omnivision OX03C10_E66Y-001D-Z.

  • 0 in reply to Rutuja Kate
    TI__Guru 58705 points

    Hi Rutuja, 

    Thanks for your question. Since Nov. 24 & Nov. 25th are US holidays, the team will resume activity on E2E upon return on Monday Nov. 28th. Thanks for your patience. 

    Regards, 

    Logan