DS92LV0422: Question about skew bwtween LVDS data pairs and LVDS clock

Mitchell Kary

Part Number: DS92LV0422
Other Parts Discussed in Thread: DS92LV0421

Hi,

I am looking for guidance on PCB trace matching between LVDS data Pairs and LVDS clock pair sometimes referred to as inter-pair skew for the DS92LV0422 deserializer andDS92LV0421 serializer. In both cases it is connected to AMD FPGA Ultrascale+.

The application notes only mention matching between lvds P/N of 30ps.

Thanks,

Mitch

over 1 year ago

0 Ben Dattilo over 1 year ago

TI__Mastermind 24455 points

Hi Mitch,

We don't have a set limit for this skew, but in general it needs to be as small as possible. I would keep to the same 30ps/5mm max intra-pair skew in the app note, since this is already a fairly large margin. Less than this would be even better. Newer devices recommend even tighter length matching ~5mils.

Regards,

Ben

0 Mitchell Kary over 1 year ago in reply to Ben Dattilo

Intellectual 630 points

Ho Ben,

Thanks for the guidance. One last question about DS92LV0421. I know the clk input is some kind of special encoding and not a normal 50/50 period. Can you point me to some documentation or provide an explanation that describes how to generate the clock properly?

-Mitch

0 Ben Dattilo over 1 year ago in reply to Mitchell Kary

TI__Mastermind 24455 points

Hi Mitch,

I don't have any documentation for this on hand, however I will see if I can find something to help explain. I am out of office tomorrow, so the earliest I'll be able to get back to you is Thursday.

Regards,

Ben

0 Ben Dattilo over 1 year ago in reply to Ben Dattilo

TI__Mastermind 24455 points

Hi Mitchell,

I can't find any information about any special encoding as you mentioned. Can you point me to where you have seen that before?

Regards,

Ben

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DS92LV0422: Question about skew bwtween LVDS data pairs and LVDS clock