• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 259 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO2001: the specific value of "slightly longer" in XIO2001 Implementation Guide

Noriyuki Takahashi
Genius 9680 points
Part Number: XIO2001

Hi team,

We can see the description "slightly longer" below in Figure 3 of XIO2001 Implementation Guide, but could you tell what is the specific value of "slightly longer"? 

>Feedback clock from CLKOUT6 should be slightly longer than the longest CLK provided to a downstream device. 

Regards,

Noriyuki Takahashi

  • 0
    TI__Mastermind 20870 points

    Hello,

    Below are the etch lengths for the clocks on the EVM.  I don't have a more specific length than "slightly longer", but I have asked design to see if they have any recommendations.

    Net Name Etch Length (mils) Manhattan Length (mils) Percent Manhattan (mils)
    PCI_FBCLK 7464.06 4628.88 161.25
    PCI_PCLK0 4950.94 1429.98 346.22
    PCI_PCLK1 4951.31 2261.47 218.94
    PCI_PCLK2 4958.32 3061.47 161.96

    Regards,

    Nicholaus

  • 0
    Guru 258490 points

    To reduce skew, the clock signal edges should arrive at the CLK pin at exactly the same time as they arrive at the other PCI devices.

    On the EVM, the FBCLK trace is 5.74 mils longer than PCLK2 (+2500 mils for the PCI connector). This conforms to the restriction that "Clocks should be length matched to each other within 10 mils."

  • 0 in reply to Clemens Ladisch
    TI__Genius 9680 points

    Hi Clemens,

    Could you tell what PCLK2 is?

    Clemens Ladisch said:
    To reduce skew, the clock signal edges should arrive at the CLK pin at exactly the same time as they arrive at the other PCI devices.

    Do you mean that it is recommended to match the length of PCLK2 and the length between CLK and CLKOUT6 to reduce skew?

    Regards,

    Noriyuki Takahashi

  • 0 in reply to Noriyuki Takahashi
    Guru 258490 points

    PCLK2 is just the name of one of the CLKOUTx nets on the EVM.

    All traces connected to CLKOUTx should be length matched.

  • 0 in reply to Clemens Ladisch
    TI__Mastermind 20870 points

    Hi Noriyuki,

    The response from design was similar.  That you would want to match all the clocks on the bus so they seem the same PCI clock at the same time as shown in the PCI 2.3 specification.  Refer to sections 4.3 and 7.7.1.

    I am double checking if there are any additional requirements specific to the XIO2001.

    Regards,

    Nicholaus

  • 0 in reply to Nicholaus_Malone
    TI__Genius 9680 points

    Nicholaus, Clemens

    Sorry, I can't understand yet.

    Question1

    Nicholaus_Malone said:
    Net Name Etch Length (mils) Manhattan Length (mils) Percent Manhattan (mils)
    PCI_FBCLK 7464.06 4628.88 161.25
    PCI_PCLK0 4950.94 1429.98 346.22
    PCI_PCLK1 4951.31 2261.47 218.94
    PCI_PCLK2 4958.32 3061.47 161.96

    According to the etch lengths for the clocks on the EVM above, PCI_PCLK0/1/2 are matched within 10mils. This follows below.  It seems PCI_FBLCK doesn't follow  "slightly longer". How should I understand this?

    Clemens Ladisch said:
    This conforms to the restriction that "Clocks should be length matched to each other within 10 mils."

    Question2

    The users guide mentions as below. For the clarification,  could you tell what the longest CLK provided to a downstream device is? 

    "Feedback clock from CLKOUT6 should be slightly longer than the longest CLK provided to a downstream device."

    Question3

    How should customer set the length of Feedback clock from CLKOUT6? This is an original question.

    Regards,

    Noriyuki Takahaashi

  • +1 in reply to Noriyuki Takahashi
    Guru 258490 points

    1. A PCI connector/card adds 2500 mils. So the total clock trace lengths of PCI_PCLK0/1/2 are 7450.94/7451.31/7458.32 mils.

    2. PCI_PCLK has 7458.32 mils.

    3. Take the longest clock trace, and add a little bit, but no more than 10 mils.