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DS90UB964-Q1: DS90UB964 rear view camera analysis

Part Number: DS90UB964-Q1

dear

 

dear 

       attachment is about DS90UB964 apply in rear view  camera ,but there is clock problem,could you help to analysis?thanks in advance

  • Hi Raymond,

    Thanks for the information.

    1. Can you please send a register dump of the issue 964 and the normal 964 so I can compare them?
    2. I noticed that you included a schematic, but it is too small for me to read closely. Can you send the 964 schematic again so I can check if there is anything wrong?

    Regards,

    Cindy

  • dear cindyt

    1. there is register dump of the issue 964 and the normal 964 in original file which free back from customer engineer

    2.attachment is about  964 SCH,please check,thanks

    UB964.pdf

  • Hello, 

    Since today is a US public holiday, we will continue support on your request on Monday. Thank you for your patience. 

    Regards, 

    Logan

  • Hi Raymond,

    To make sure I understand, you are trying to get a CSI rate of 400Mbps, but when you set 0x1F = 0x03 the rate change does not take effect? This is because 400Mbps is a special case and you need to program additional registers. When configuring 800Mbps or 1.6Mbps, the CSI-2 timing parameters are automatically set based on 0x1F. For 400Mbps, you need to manually program the CSI-2 timing parameters and the appropriate override bit needs to be set. Please see section 8.4.15 in the 964 datasheet to see how to configure the additional registers. This should help you achieve the correct CSI-2 rate. 

    Regards,

    Cindy

  • Hi Cindy,

    If we only set 0x1F=0x03 for 400Mbps, what is the problem on this? Some abnormal display issue?

    We found for 964 chips with 400Mbps setting, most of chips work good, but for 2 out of them, the CSI rate will increase from 400Mbps to 1.2xGbps, cause black screen issue. Can you share why the issue will occur on particular 964 chips? 

    Johnny

  • Hi Johnny,

    We recommend setting the extra timing registers for 400Mbps even if it seems to work for other chips because this is how we have validated it to comply with the MIPI specifications. The timing parameters are required in order to use 400Mbps, so not following these steps could cause CSI-2 video timing issues at that rate. All I can share is that datasheet requirements must be followed in order to get intended performance across devices.

    Regards,

    Cindy

  • Hi cindy

    attachment is about Rear view camera black screen analysis  and 964 SCH from customer xiaopeng,update lastest test condition,please help to check,thanks

    Rear view camera black screen analysis(2).docx

    0601.UB964.pdf

  • Hi Raymond,

    Here are my comments on the schematic: 

    • For the PDB pin in the schematic, there should be a 10kOhm pull-up resistor to 1.8V and a >10uF capacitor to ground (see Typical Application diagram in 964 datasheet). This is important in order to ensure that the power-up sequence is followed. If you are relying on the external RC circuit to drive PDB, you will need to fix this in the schematic.
    • There is no ferrite bead recommended in the datasheet for the VDDIO pin. I see the document says there is no abnormal power supply, but please confirm that VDDIO is within spec since this pin does not exactly follow the datasheet. 

    I see for the power-up sequence waveform you just show the power up of 1.1V and 1.8V. Can you also probe VDDIO and PDB and make sure that the entire power-up sequence is followed in Section 10.2?

    Comparing the good.txt and bad.txt register dump, the only difference is with the FPD-Link packet frequency in registers 0x4F and 0x50. These registers read back the effective FPD3_PCLK frequency which depends on the operating mode (see note 2 in UB964 datasheet on page 10). Refer to this E2E for more information on how it is calculated. Can you confirm that the PCLK on the serializer is stable and meeting datasheet requirements? 

    Regards,

    Cindy

  • 1.  PDB on board is controlled by software, the time of raising PDB is far behind the time of power supply stabilization (more than 200ms) , which meets the requirement of manual completely

    2. VDDIO series magnetic beads are good for filtering high frequency harmonics, to improve the quality of power supply, the actual test did not meet the requirements of the manual. The whole circuit design is evaluated and approved by TI.

    3. Make sure that the FTP link is OK, that ABA cross-validation has been done, and that the configuration is OK.

    any advice?thanks in advance

  • Hi Raymond,

    Thank you for the clarification on the schematic.

    I noticed in the register configs that you have continuous clock mode turned off in register 0x33. For debugging purposes, can you try enabling continuous clock mode and then measure the CSI clock output on the scope to see if it is still drifting in frequency? 

    For the register dump of the issue unit (bad.txt), what do you mean by "the failed machine reads at the time of replay?" Were these registers read when the CSI clock reached the high frequency and the screen went black?

    Are these units tested over temperature, or were these measurements taken at room temp?  

    Regards,

    Cindy