Hi team,
One of our customer's issues, I'm forwarding it below, please give your comments if any.
The DP83640 is configured in 100M, full duplex mode. The triple-speed Ethernet IP core in FPGA that interacts with it occasionally reports CRC errors when sending and receiving data simultaneously. The reason for this error is that the frame length field value (such as 800) in the header of the erroneous frame is inconsistent with the actual number of bytes in the frame (such as 21). So what is the reason for this inconsistency
Best Regards,
Amy Luo
