Downstream IC needs at least 15 Mhz PCLK, but currently the PCLK is around 11 Mhz. When we cannot change the design on the serializer side, is there a way to increase the output PCLK?
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Downstream IC needs at least 15 Mhz PCLK, but currently the PCLK is around 11 Mhz. When we cannot change the design on the serializer side, is there a way to increase the output PCLK?
Hi Wei,
Unfortunately there is no way to change the PCLK within the Ser/Des. It's recommended to use that exact PCLK needed for the downstream device at the Ser input side.
Regards,
Fadi A.