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TLK10232: 10G link failure

Panayotis Tziaros
Prodigy 40 points
Part Number: TLK10232

Hello,

We have used TLK10232 dual phy component for a XAUI to SFP/SFP+ application and we have problem in 10G link establishment.

The initialization of the device is shown below:

  • Reset device (assert RESET_N pin)
  • Select the reference clock selection (312.5 MHz)
  • Disable auto-negotiation
  • Disable link training
  • Write 16’h03FF to 0x1E.8020
  • Write HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101
  • Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3

The peer device is a VIAVI MTS5800 Tester.

The inventory info of the SFP used are:

Inventory:
    Identifier                                : 0x03 (SFP)
    Extended identifier                       : 0x04 (GBIC/SFP defined by 2-wire interface ID)
    Connector                                 : 0x07 (LC)
    Transceiver codes                         : 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
    Transceiver type                          : 10G Ethernet: 10G Base-SR
    Encoding                                  : 0x06 (64B/66B)
    BR, Nominal                               : 10300MBd
    Rate identifier                           : 0x00 (unspecified)
    Length (SMF,km)                           : 0km
    Length (SMF)                              : 0m
    Length (50um)                             : 80m
    Length (62.5um)                           : 30m
    Length (Copper)                           : 0m
    Length (OM3)                              : 300m
    Laser wavelength                          : 850nm
    Vendor name                               : FIBRAIN
    Vendor OUI                                : 00:1b:c5
    Vendor PN                                 : FTFM1XGS85L30MDI
    Vendor rev                                : 1.0
    Option values                             : 0x00 0x1a
    Option                                    : RX_LOS implemented
    Option                                    : TX_FAULT implemented
    Option                                    : TX_DISABLE implemented
    BR margin, max                            : 0%
    BR margin, min                            : 0%
    Vendor SN                                 : CIC20210038
    Date code                                 : 200514

Tester detects signal present but no link and indicates "Local Fault Detect"

See below some register values of the TLK10232 PHY:

0x1e.0000=0x610 (GLOBAL_CONTROL_1)
0x1e.0001=0xba4 (CHANNEL_CONTROL_1)

0x1e.001d=0x1000 (HS_CH_CONTROL_1)

0x07.0000=0x2000 (AN_CONTROL)
0x01.0096=0x0 (LT_TRAIN_CONTROL)
0x1e.8020=0x3ff (TI_RESERVED_CONTROL)
0x1e.0004=0x5500 (HS_SERDES_CONTROL_3)

0x01.0001=0x6 (PMA_STATUS_1)
0x01.0008=0x3000 (PMA_STATUS_2)
0x01.000a=0x1 (PMA_RX_SIGNAL_DET_STATUS)
0x03.0001=0x86 (PCS_STATUS_1)
0x03.0008=0x1 (PCS_STATUS_2)
0x03.0020=0x1005 (KR_PCS_STATUS_1)
0x03.0021=0x0 (KR_PCS_STATUS_2)

Can you give us some help to find out the problem?

Thanks in advance

  • 0
    TI__Mastermind 19185 points

    Hi, see suggestions below.

    • I would recommend to double check your TLK I/O pin settings including,
      • Ensure PRBSEN is low for Standard Ethernet link testing
      • Make sure device is not placed in test mode or held in reset state
      • Ensure the device is set to 10G-KR mode via MODE_SEL and ST pins 
    • I've attached as reference a GUI configuration text file containing SerDes settings for 10G KR case. I would recommend to compare these settings with what you are implementing, noting of course that link training and auto-neg must be disabled for the XAUI to SFP+ interface case.
    • TLK10232_10GKR_Mode_With_Auto_Negotiation_Link_Training_Apply_Settings_Script.txt 
      //********************************************************************************************
//                                                                             
//                      Copyright Texas Instruments Inc                        
//                  TI Proprietary Information Internal Data                   
// This is a general provisioning script for the TLK10232 Apply Settings Portion of the GUI
//                                            
// Author:  Jonathan Nerger                                                  
// Modified Date:  April 01, 2013                               
// Revision: Rev 0.2                                                  
//********************************************************************************************


//********************************************************************************************
//                            Script Command Parameter Reference
//********************************************************************************************
//SET BOARD(BOARD_NUMBER)
//MDIO45 WRITE (CHANNEL_NAME,&REGISTERNAME)
//MDIO45 WRITE IMM (CH_ADDR,DEVICE_ADDR,REGISTER_ADDR,REGISTER_VALUE)
//MDIO45 READ (CHANNEL_NAME,&REGISTERNAME)
//MDIO45 READ UNTIL (CHANNEL_NAME,&REGISTERNAME,MASK,EXPECTED,TIMEOUT(ms))
//MDIO45 READ IMM(CH_ADDR,DEVICE_ADDR,REGISTER_ADDR,MASK,EXPECTED,TIMEOUT(ms))
//I2C WRITE (&REGISTER_NAME)
//I2C WRITE IMM (DEVICE_ADDRESS,REGISTER_ADDRESS, REGISTER_VALUE )
//I2C READ (&REGISTER_NAME)
//I2C READ UNTIL (&REGISTER_NAME, MASK, EXPECTED,TIMEOUT(ms))
//I2C READ IMM (DEVICE_ADDRESS,REGISTER_ADDRESS, MASK, EXPECTED,TIMEOUT(ms))
//DELAY			//This reads the test time per parameter field in the HS Link Optimizer and waits that amount of time
//WAIT(time ms)
//MDIO45 WRITE FUNC (CHANNEL_NAME, FIELD_NAME, Data[in hex])


//********************************************************************************************
//                            CDCM6208 Clock Generator Configuration
//********************************************************************************************
// Configure the Primary/Secondary Oscillator Enable Pins
I2C WRITE (REGISTER_04)
// Wait 100mS
WAIT(100)

// Disable the CDCM6208 during configuration
I2C WRITE FUNC (I2C_RESETN/PWR,0x0)
// Wait 100mS
WAIT(100)

//Configure the CDCM6208 Registers
SPI WRITE (CLK_REGISTER_0)
SPI WRITE (CLK_REGISTER_1)
SPI WRITE (CLK_REGISTER_2)
SPI WRITE (CLK_REGISTER_3)
SPI WRITE (CLK_REGISTER_4)
SPI WRITE (CLK_REGISTER_5)
SPI WRITE (CLK_REGISTER_6)
SPI WRITE (CLK_REGISTER_7)
SPI WRITE (CLK_REGISTER_8)
SPI WRITE (CLK_REGISTER_9)
SPI WRITE (CLK_REGISTER_10)
SPI WRITE (CLK_REGISTER_11)
SPI WRITE (CLK_REGISTER_12)
SPI WRITE (CLK_REGISTER_13)
SPI WRITE (CLK_REGISTER_14)
SPI WRITE (CLK_REGISTER_15)
SPI WRITE (CLK_REGISTER_16)
SPI WRITE (CLK_REGISTER_17)
SPI WRITE (CLK_REGISTER_18)
SPI WRITE (CLK_REGISTER_19)
SPI WRITE (CLK_REGISTER_20)
//SPI WRITE (CLK_REGISTER_21)
//SPI WRITE (CLK_REGISTER_40)

//Enable the CDCM6208 after the configuration is complete
I2C WRITE FUNC (I2C_RESETN/PWR,0x1)

//********************************************************************************************
//                            TLK10232 Soft Reset and Mode Configuration
//********************************************************************************************
// Configure MODE_SEL and ST Pins
I2C WRITE (REGISTER_05)

// Wait 100mS
WAIT(100)

// Soft Reset & disable global config
MDIO45 WRITE FUNC (GLOBAL,GLOBAL_RESET,0x1)
MDIO45 WRITE FUNC (GLOBAL,GLOBAL_RESET,0x0)
MDIO45 WRITE (GLOBAL,GLOBAL_CONTROL_1)

// Configure Operating Mode Registers
MDIO45 WRITE (A,CHANNEL_CONTROL_1)
MDIO45 WRITE (A,AN_CONTROL)
MDIO45 WRITE (B,CHANNEL_CONTROL_1)
MDIO45 WRITE (B,AN_CONTROL)


//********************************************************************************************
//                            Switch Provisioning
//********************************************************************************************
//Configure CHA TX Switch
MDIO45 WRITE (A,DST_CONTROL_1)
MDIO45 WRITE (A,DST_CONTROL_2)
MDIO45 WRITE (A,DST_ON_CHAR_CONTROL)
MDIO45 WRITE (A,DST_OFF_CHAR_CONTROL)
MDIO45 WRITE (A,DST_STUFF_CHAR_CONTROL)

//Configure CHA RX Switch
MDIO45 WRITE (A,DSR_CONTROL_1)
MDIO45 WRITE (A,DSR_CONTROL_2)
MDIO45 WRITE (A,DSR_ON_CHAR_CONTROL)
MDIO45 WRITE (A,DSR_OFF_CHAR_CONTROL)
MDIO45 WRITE (A,DSR_STUFF_CHAR_CONTROL)

//Configure CHB TX Switch
MDIO45 WRITE (B,DST_CONTROL_1)
MDIO45 WRITE (B,DST_CONTROL_2)
MDIO45 WRITE (B,DST_ON_CHAR_CONTROL)
MDIO45 WRITE (B,DST_OFF_CHAR_CONTROL)
MDIO45 WRITE (B,DST_STUFF_CHAR_CONTROL)

//Configure CHB RX Switch
MDIO45 WRITE (B,DSR_CONTROL_1)
MDIO45 WRITE (B,DSR_CONTROL_2)
MDIO45 WRITE (B,DSR_ON_CHAR_CONTROL)
MDIO45 WRITE (B,DSR_OFF_CHAR_CONTROL)
MDIO45 WRITE (B,DSR_STUFF_CHAR_CONTROL)

//********************************************************************************************
//                            Set Default HS TX Settings loading and LT Controls
//********************************************************************************************

MDIO45 WRITE IMM (0x0,0x07,0x0000,0x2000)
MDIO45 WRITE IMM (0x0,0x1E,0x0096,0x0000)
MDIO45 WRITE IMM (0x0,0x1E,0x000E,0x0008)
MDIO45 WRITE IMM (0x0,0x1E,0x9000,0x024D)
MDIO45 WRITE IMM (0x0,0x1E,0x8101,0x0004)
MDIO45 WRITE IMM (0x0,0x1E,0x8100,0x0004)
MDIO45 WRITE IMM (0x0,0x1E,0x8100,0x0000)
MDIO45 WRITE IMM (0x0,0x1E,0x9001,0x0200)
MDIO45 WRITE IMM (0x0,0x07,0x0000,0x3000)
MDIO45 WRITE IMM (0x0,0x1E,0x0096,0x0002)
MDIO45 WRITE IMM (0x0,0x1E,0x9005,0x1C00)

MDIO45 WRITE IMM (0x1,0x07,0x0000,0x2000)
MDIO45 WRITE IMM (0x1,0x1E,0x0096,0x0000)
MDIO45 WRITE IMM (0x1,0x1E,0x000E,0x0008)
MDIO45 WRITE IMM (0x1,0x1E,0x9000,0x024D)
MDIO45 WRITE IMM (0x1,0x1E,0x8101,0x0004)
MDIO45 WRITE IMM (0x1,0x1E,0x8100,0x0004)
MDIO45 WRITE IMM (0x1,0x1E,0x8100,0x0000)
MDIO45 WRITE IMM (0x1,0x1E,0x9001,0x0200)
MDIO45 WRITE IMM (0x1,0x07,0x0000,0x3000)
MDIO45 WRITE IMM (0x1,0x1E,0x0096,0x0002)
MDIO45 WRITE IMM (0x1,0x1E,0x9005,0x1C00)

//********************************************************************************************
//                            CH A Provisioning
//********************************************************************************************

MDIO45 WRITE (A,CHANNEL_CONTROL_1)
MDIO45 WRITE (A,HS_SERDES_CONTROL_1)
MDIO45 WRITE (A,HS_SERDES_CONTROL_2)
MDIO45 WRITE (A,HS_SERDES_CONTROL_3)
MDIO45 WRITE (A,HS_SERDES_CONTROL_4)
MDIO45 WRITE (A,LS_SERDES_CONTROL_1)
MDIO45 WRITE (A,LN3_LS_SERDES_CONTROL_2)
MDIO45 WRITE (A,LN2_LS_SERDES_CONTROL_2)
MDIO45 WRITE (A,LN1_LS_SERDES_CONTROL_2)
MDIO45 WRITE (A,LN0_LS_SERDES_CONTROL_2)
MDIO45 WRITE (A,LN3_LS_SERDES_CONTROL_3)
MDIO45 WRITE (A,LN2_LS_SERDES_CONTROL_3)
MDIO45 WRITE (A,LN1_LS_SERDES_CONTROL_3)
MDIO45 WRITE (A,LN0_LS_SERDES_CONTROL_3)
MDIO45 WRITE (A,HS_OVERLAY_CONTROL)
MDIO45 WRITE (A,LS_OVERLAY_CONTROL)
MDIO45 WRITE (A,LOOPBACK_TP_CONTROL)
MDIO45 WRITE (A,LS_CONFIG_CONTROL)
MDIO45 WRITE (A,CLK_CONTROL)
MDIO45 WRITE (A,LN3_LS_CH_CONTROL_1)
MDIO45 WRITE (A,LN2_LS_CH_CONTROL_1)
MDIO45 WRITE (A,LN1_LS_CH_CONTROL_1)
MDIO45 WRITE (A,LN0_LS_CH_CONTROL_1)
MDIO45 WRITE (A,HS_CH_CONTROL_1)
MDIO45 WRITE (A,VS_10G_LN_ALIGN_ACODE_P)
MDIO45 WRITE (A,VS_10G_LN_ALIGN_ACODE_N)
MDIO45 WRITE (A,AUTO_CLKOUT_CONTROL)
MDIO45 WRITE (A,LATENCY_MEASURE_CONTROL)
MDIO45 WRITE (A,TRIGGER_LOAD_CONTROL)
MDIO45 WRITE (A,TRIGGER_EN_CONTROL)

MDIO45 WRITE (A,PMA_CONTROL_1)
MDIO45 WRITE (A,LT_TRAIN_CONTROL)
MDIO45 WRITE (A,KR_FEC_CONTROL)
MDIO45 WRITE (A,KR_VS_FIFO_CONTROL_1)
MDIO45 WRITE (A,KR_VS_TP_GEN_CONTROL)
MDIO45 WRITE (A,KR_VS_TP_VER_CONTROL)
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN0)
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN1)
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN2)
MDIO45 WRITE (A,KR_VS_CTC_ERR_CODE_LN3)

MDIO45 WRITE (A,PCS_CONTROL)
MDIO45 WRITE (A,PCS_TP_SEED_A0)
MDIO45 WRITE (A,PCS_TP_SEED_A1)
MDIO45 WRITE (A,PCS_TP_SEED_A2)
MDIO45 WRITE (A,PCS_TP_SEED_A3)
MDIO45 WRITE (A,PCS_TP_SEED_B0)
MDIO45 WRITE (A,PCS_TP_SEED_B1)
MDIO45 WRITE (A,PCS_TP_SEED_B2)
MDIO45 WRITE (A,PCS_TP_SEED_B3)
MDIO45 WRITE (A,PCS_TP_CONTROL)
MDIO45 WRITE (A,PCS_VS_CONTROL)
MDIO45 WRITE (A,AN_CONTROL)
MDIO45 WRITE (A,AN_ADVERTISEMENT_1)
MDIO45 WRITE (A,AN_ADVERTISEMENT_2)
MDIO45 WRITE (A,AN_ADVERTISEMENT_3)
MDIO45 WRITE (A,AN_XNP_TRANSMIT_1)
MDIO45 WRITE (A,AN_XNP_TRANSMIT_2)
MDIO45 WRITE (A,AN_XNP_TRANSMIT_3)


//********************************************************************************************
//                            CH B Provisioning
//********************************************************************************************

MDIO45 WRITE (B,CHANNEL_CONTROL_1)
MDIO45 WRITE (B,HS_SERDES_CONTROL_1)
MDIO45 WRITE (B,HS_SERDES_CONTROL_2)
MDIO45 WRITE (B,HS_SERDES_CONTROL_3)
MDIO45 WRITE (B,HS_SERDES_CONTROL_4)
MDIO45 WRITE (B,LS_SERDES_CONTROL_1)
MDIO45 WRITE (B,LN3_LS_SERDES_CONTROL_2)
MDIO45 WRITE (B,LN2_LS_SERDES_CONTROL_2)
MDIO45 WRITE (B,LN1_LS_SERDES_CONTROL_2)
MDIO45 WRITE (B,LN0_LS_SERDES_CONTROL_2)
MDIO45 WRITE (B,LN3_LS_SERDES_CONTROL_3)
MDIO45 WRITE (B,LN2_LS_SERDES_CONTROL_3)
MDIO45 WRITE (B,LN1_LS_SERDES_CONTROL_3)
MDIO45 WRITE (B,LN0_LS_SERDES_CONTROL_3)
MDIO45 WRITE (B,HS_OVERLAY_CONTROL)
MDIO45 WRITE (B,LS_OVERLAY_CONTROL)
MDIO45 WRITE (B,LOOPBACK_TP_CONTROL)
MDIO45 WRITE (B,LS_CONFIG_CONTROL)
MDIO45 WRITE (B,CLK_CONTROL)
MDIO45 WRITE (B,LN3_LS_CH_CONTROL_1)
MDIO45 WRITE (B,LN2_LS_CH_CONTROL_1)
MDIO45 WRITE (B,LN1_LS_CH_CONTROL_1)
MDIO45 WRITE (B,LN0_LS_CH_CONTROL_1)
MDIO45 WRITE (B,HS_CH_CONTROL_1)
MDIO45 WRITE (B,VS_10G_LN_ALIGN_ACODE_P)
MDIO45 WRITE (B,VS_10G_LN_ALIGN_ACODE_N)
MDIO45 WRITE (B,AUTO_CLKOUT_CONTROL)
MDIO45 WRITE (B,LATENCY_MEASURE_CONTROL)
MDIO45 WRITE (B,TRIGGER_LOAD_CONTROL)
MDIO45 WRITE (B,TRIGGER_EN_CONTROL)

MDIO45 WRITE (B,PMA_CONTROL_1)
MDIO45 WRITE (B,LT_TRAIN_CONTROL)
MDIO45 WRITE (B,KR_FEC_CONTROL)
MDIO45 WRITE (B,KR_VS_FIFO_CONTROL_1)
MDIO45 WRITE (B,KR_VS_TP_GEN_CONTROL)
MDIO45 WRITE (B,KR_VS_TP_VER_CONTROL)
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN0)
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN1)
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN2)
MDIO45 WRITE (B,KR_VS_CTC_ERR_CODE_LN3)

MDIO45 WRITE (B,PCS_CONTROL)
MDIO45 WRITE (B,PCS_TP_SEED_A0)
MDIO45 WRITE (B,PCS_TP_SEED_A1)
MDIO45 WRITE (B,PCS_TP_SEED_A2)
MDIO45 WRITE (B,PCS_TP_SEED_A3)
MDIO45 WRITE (B,PCS_TP_SEED_B0)
MDIO45 WRITE (B,PCS_TP_SEED_B1)
MDIO45 WRITE (B,PCS_TP_SEED_B2)
MDIO45 WRITE (B,PCS_TP_SEED_B3)
MDIO45 WRITE (B,PCS_TP_CONTROL)
MDIO45 WRITE (B,PCS_VS_CONTROL)
MDIO45 WRITE (B,AN_CONTROL)
MDIO45 WRITE (B,AN_ADVERTISEMENT_1)
MDIO45 WRITE (B,AN_ADVERTISEMENT_2)
MDIO45 WRITE (B,AN_ADVERTISEMENT_3)
MDIO45 WRITE (B,AN_XNP_TRANSMIT_1)
MDIO45 WRITE (B,AN_XNP_TRANSMIT_2)
MDIO45 WRITE (B,AN_XNP_TRANSMIT_3)


//********************************************************************************************
//                            Restart Auto Negotiation
//********************************************************************************************

// Issue Auto Negotiate Reset 
MDIO45 WRITE FUNC (A,AN_RESTART,0x1)
MDIO45 READ (A,AN_CONTROL)
MDIO45 WRITE FUNC (B,AN_RESTART,0x1)
MDIO45 READ (B,AN_CONTROL)


// The AN_RESTART bit is self clearing, but the GUI is not. Reset the bit in the GUI.
// Not required in the customer's system application
MDIO45 WRITE FUNC (A,AN_RESTART,0x0)
MDIO45 WRITE FUNC (B,AN_RESTART,0x0)


// Wait 2000mS
WAIT(2000)

//********************************************************************************************
//                            Verify HS_AZ_DONE, HS_AGC_LOCKED and LS/HS PLL Lock Status
//********************************************************************************************

// Poll LS/HS_PLL_LOCK,HS_AZ_DONE,HS_AGC_LOCKED Bits
MDIO45 READ UNTIL (A,CHANNEL_STATUS_1,0x1803,0x1803,1000)
MDIO45 READ UNTIL (B,CHANNEL_STATUS_1,0x1803,0x1803,1000)

//********************************************************************************************
//                            Verify Auto Negotiation Complete
//********************************************************************************************

// Poll AN_COMPLETE,LINK_STATUS Bits
MDIO45 READ UNTIL (A,AN_STATUS,0x0024,0x0024,1000)
MDIO45 READ UNTIL (B,AN_STATUS,0x0024,0x0024,1000)

//********************************************************************************************
//                            Verify Link Training Complete
//********************************************************************************************

// Poll KR_TRAINING_FAIL,KR_RX_STATUS Bits
MDIO45 READ UNTIL (A,LT_TRAIN_STATUS,0x0009,0x0001,1000)
MDIO45 READ UNTIL (B,LT_TRAIN_STATUS,0x0009,0x0001,1000)

//********************************************************************************************
//                            Verify 10GKR Mode
//********************************************************************************************

// Poll AN_10G_KR Bit
MDIO45 READ UNTIL (A,AN_BP_STATUS,0x0008,0x0008,1000)
MDIO45 READ UNTIL (B,AN_BP_STATUS,0x0008,0x0008,1000)

//********************************************************************************************
//                            Clear Status Registers and Error Counters
//********************************************************************************************

// Read and Clear Latched Status Register Bits
MDIO45 READ (A,CHANNEL_STATUS_1)
MDIO45 READ (B,CHANNEL_STATUS_1)

// Read and Clear Error Counters
MDIO45 READ (A,HS_ERROR_COUNTER)
MDIO45 READ (B,HS_ERROR_COUNTER)

MDIO45 READ (A,LS_LN0_ERROR_COUNTER)
MDIO45 READ (B,LS_LN0_ERROR_COUNTER)

MDIO45 READ (A,LS_LN1_ERROR_COUNTER)
MDIO45 READ (B,LS_LN1_ERROR_COUNTER)

MDIO45 READ (A,LS_LN2_ERROR_COUNTER)
MDIO45 READ (B,LS_LN2_ERROR_COUNTER)

MDIO45 READ (A,LS_LN3_ERROR_COUNTER)
MDIO45 READ (B,LS_LN3_ERROR_COUNTER)

// Read and Clear Latched Status Register Bits
MDIO45 READ (A,LN0_LS_STATUS_1)
MDIO45 READ (A,LN1_LS_STATUS_1)
MDIO45 READ (A,LN2_LS_STATUS_1)
MDIO45 READ (A,LN3_LS_STATUS_1)

MDIO45 READ (B,LN0_LS_STATUS_1)
MDIO45 READ (B,LN1_LS_STATUS_1)
MDIO45 READ (B,LN2_LS_STATUS_1)
MDIO45 READ (B,LN3_LS_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO45 READ (A,PMA_STATUS_1)
MDIO45 READ (B,PMA_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO45 READ (A,PMA_STATUS_2)
MDIO45 READ (B,PMA_STATUS_2)

// Read and Clear Latched Status Register Bits
MDIO45 READ (A,PCS_STATUS_1)
MDIO45 READ (B,PCS_STATUS_1)

// Read and Clear Latched Status Register Bits
MDIO45 READ (A,PCS_STATUS_2)
MDIO45 READ (B,PCS_STATUS_2)

//********************************************************************************************
//                            Operational Mode Status
//********************************************************************************************

// Read and Verify the Operational Mode Status
MDIO45 READ UNTIL (A,CHANNEL_STATUS_1,0xFFFF,0x5C03,0)
MDIO45 READ UNTIL (B,CHANNEL_STATUS_1,0xFFFF,0x5C03,0)

MDIO45 READ UNTIL (A,HS_ERROR_COUNTER,0xFFFF,0x0000,0)
MDIO45 READ UNTIL (B,HS_ERROR_COUNTER,0xFFFF,0x0000,0)

MDIO45 READ UNTIL (A,LS_LN0_ERROR_COUNTER,0xFFFF,0x0000,0)
MDIO45 READ UNTIL (B,LS_LN0_ERROR_COUNTER,0xFFFF,0x0000,0)

MDIO45 READ UNTIL (A,LS_LN1_ERROR_COUNTER,0xFFFF,0x0000,0)
MDIO45 READ UNTIL (B,LS_LN1_ERROR_COUNTER,0xFFFF,0x0000,0)

MDIO45 READ UNTIL (A,LS_LN2_ERROR_COUNTER,0xFFFF,0x0000,0)
MDIO45 READ UNTIL (B,LS_LN2_ERROR_COUNTER,0xFFFF,0x0000,0)

MDIO45 READ UNTIL (A,LS_LN3_ERROR_COUNTER,0xFFFF,0x0000,0)
MDIO45 READ UNTIL (B,LS_LN3_ERROR_COUNTER,0xFFFF,0x0000,0)

MDIO45 READ UNTIL (A,LN0_LS_STATUS_1,0x0508,0x0100,0)
MDIO45 READ UNTIL (A,LN1_LS_STATUS_1,0x0508,0x0100,0)
MDIO45 READ UNTIL (A,LN2_LS_STATUS_1,0x0508,0x0100,0)
MDIO45 READ UNTIL (A,LN3_LS_STATUS_1,0x0508,0x0100,0)

MDIO45 READ UNTIL (B,LN0_LS_STATUS_1,0x0508,0x0100,0)
MDIO45 READ UNTIL (B,LN1_LS_STATUS_1,0x0508,0x0100,0)
MDIO45 READ UNTIL (B,LN2_LS_STATUS_1,0x0508,0x0100,0)
MDIO45 READ UNTIL (B,LN3_LS_STATUS_1,0x0508,0x0100,0)

MDIO45 READ UNTIL (A,PMA_STATUS_1,0x0084,0x0004,0)
MDIO45 READ UNTIL (B,PMA_STATUS_1,0x0084,0x0004,0)

MDIO45 READ UNTIL (A,PCS_STATUS_1,0x0084,0x0004,0)
MDIO45 READ UNTIL (B,PCS_STATUS_1,0x0084,0x0004,0)

    Regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 40 points

    Thanks for your help, we had MDIO access issue, after fixing this the link came up.