DP83825I: Custom Hardware Schematic review request

Hi Josh,

Let me review the schematic and get back to you by Wednesday next week.

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Regards,
Gokul.

Hey Gokul, 

Thanks for agreeing to review the PHY - do you have any recommendations?

Hi Josh,

PFA, the schematic with annotated comments.

AM6232_DP83825i_feedback_gokul.pdf

Josh Green said:

- Is the CLKOUT0/EXT_REFCLK1 50MHz outptu fromthe sitara correctly connected to the PHY and also RMII interface?

The reference clock is connected to the PHY correctly for a RMII Slave PHY to RMII Slave MAC configuration. Can you please check with AM62 team if the connections are appropriate to AM62?

Josh Green said:

Are there any timing constraints on the 50MHz signals going to the OSCIN of the phy and the RMII_RXC pin?

You can refer to 'Power-Up Timing' recommendations in the datasheet. I see that RESET_N recommendation is already implemented.

Josh Green said:

- The PHY should be slave mode as the external clock can only be set for 50MHz. Is the strapping correct for this?

Yes.

Please let me know if you need more details.

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Regards,
Gokul.

Hi Gokul,

Many thanks for the review comments :)

I did wonder whether the oscillator could remain at +3V3 with a VDDIO of +1V8, but this section in the datasheet made me think it wasn't possible?

I'll get the decoupling and pull-down changed and ask the AM62 team to have a look at the RMII/clocking setup.

Thanks again!