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TLK10081: Occasional unexpected sequence detected on high-speed output

Alexander Evers
Prodigy 10 points
Part Number: TLK10081

Hi,

We have a setup where we aggregate 8x625 Mbps links to 1x5.00 Gbps link. We only use the TLK10081 in TX mode.
With the data generator chip in idle mode it generates 0xBC characters. We configured the TLK10081 to replace this charackter with 0x5C on lane 0. This all looks fine and we receive the 0xBC and 0x5C characters on our fpga.
But when we trigger on our FPGA on not the 0xBC char (note that we have replaced the 0x5C with 0xBC again inside the FPGA) we get occasionally a pattern of
"6x 0xFE - 4x"idle char" (0xFD in our case) - 1x 0xFE". Those chars are all marked as control characters.

The sequence we get: /K30.7/K30.7/K30.7/K30.7/K30.7/K30.7/K29.7/K29.7/K29.7/K29.7/K30.7/

our TLK configuration is:

{ TLK81_GLOBAL_CONTROL, 0x8610 },      // Reset
{ TLK81_CHANNEL_CONTROL, 0x0000 },     // Disable link training
{ TLK81_HS_SERDES_CONTROL_1, 0x8315 }, // Set PLL multiplier to 8x
{ TLK81_HS_SERDES_CONTROL_2, 0xA940 }, /* Set HS TX rate to half rate
                                          Disable HS RX */
{ TLK81_HS_SERDES_CONTROL_3, 0x1540 }, // Disables high frequency peaking.
{ TLK81_HS_TP_CONTROL, 0x0520 },       /* Disable HS Test Pattern (0x2520)(0x2200)(0x2020)(0x0520)
                                          Set HS tp 2^7
                                          Set LS PRBS 2^7
                                          Disable Deep Remote Loopback */
{ TLK81_LS_SERDES_CONTROL_1, 0x8110 },  // Set LS_MPY to 4 times
{ TLK81_LS_CH_CONTROL, 0x0001},
{ TLK81_LS_SERDES_CONTROL_2, 0xDE02},   /* Set LS PLL to quarter rate
                                           Disable LS_RX_ENTX to turn off LS transmitter*/
{ TLK81_CLK_CONTROL, 0x0080 },          // CLKOUTxP/N disable
{ TLK81_HS_ALIGN_CODE_CONTROL, 0x02BC },// Set TX marker selection on lane 0
{ TLK81_HS_CH_CONTROL, 0x0880 },        // Enable TX marker replace
 
{ TLK81_EXT_ADDRESS_CONTROL, TLK81EXT_VS_TX_MARKER_REPLACE_CHAR },
{ TLK81_EXT_ADDRESS_DATA, 0x25C },      // TX replace char 0x25C

{ TLK81_EXT_ADDRESS_CONTROL, TLK81EXT_VS_TX_IDLE_P_CHAR },
{ TLK81_EXT_ADDRESS_DATA, 0x2FD },      // TX idle Pchar

{ TLK81_EXT_ADDRESS_CONTROL, TLK81EXT_VS_TX_IDLE_N_CHAR },
{ TLK81_EXT_ADDRESS_DATA, 0x2FD },      // TX idle Nchar

{ TLK81_RESET_CONTROL, 0x0008 }         // DATAPATH_RESET

And this is what we get after we perform lane deinterleaving in the FPGA:

zoomed in on 1 sequence

We suspect that this happens due to clock tolerance compensation. But then we would expect a single idle character (0xFD). So why is it not a single 0xFD character and why do we get a few 0xFE characters as well?  

Thanks in advance.

~Alexander

  • 0
    TI__Mastermind 20192 points

    Hi Alexander,

    Thank you for the detailed explanation and commented configuration.  If you readback CHANNEL_STATUS_1 and LS_STATUS_1, what values do you get?  Do you happen to see FIFO underflow or overflow?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hi Drew,
    Thanks for your very quick response.

    Channel Status:
    If I run CHANNEL_STATUS_1 four times quickly (repeating with about 1sec interval), I get:
    ------
    0x0200
    0x0003
    0x0003
    0x0203
    ------
    0x0203
    0x0203
    0x0003
    0x0203
    ------
    "From this data, it looks like HS_PLL and LS_PLL are correctly locked and stable."

    Low-speed Status:
    For LS_STATUS_1, the eight links have the same behavior, so I will report only link 0.
    When I run LS_STATUS_1 four times quickly (repeating with about 1sec interval), I get:
    ------
    0x0844
    0x0140
    0x0140
    0x0140
    ------
    0x0144
    0x0140
    0x0140
    0x0140
    ------
    0x0144
    0x0140
    0x0144
    0x0140
    ------

    "From this data, it looks like LS_TX_FIFO_OVERFLOW latches high quite often."

    Error codes:
    datasheet page 46 notes the 0x2FE character as FIFO error codes for LS and HS.
    I've changed the LS_TX_ERROR_CODE and this changes the sequence: the first six bytes are now the new character, the last character is still the old error code (0xFE). Changing LS_RX_ERROR_CODE, HS_RX_ERROR_CODE or HS_TX_ERROR_CODE does not affect it.
    6x 0xFB (the new character) - 4x 'idle char' (0xFD in our case) - 1x 0xFE (the old character).

    The sequence is now:
    /K27.7/K27.7/K27.7/K27.7/K27.7/K27.7/K29.7/K29.7/K29.7/K29.7/K30.7/

    Why is the FIFO filling up while we're only receiving K28.5 characters which can be dropped, right?
    And what is the exact meaning of the LS_TX_ERROR_CODE?
    And what can cause the K30.7 character to show up? The datasheet not specify any other register where 0x2FE could be inserted.

    Thanks,
    ~Alexander

  • 0 in reply to Alexander Evers
    TI__Mastermind 20192 points

    Hi Alexander,

    Thanks for sharing the values of these registers.

    I currently do not have a hypothesis as to why K30.7 character is showing up.  Since this is occuring after FIFO error, I'm hopeful that this will be fixed after addressing FIFO issue.

    Regarding the FIFO issue, the most basic cause of FIFO underflow/overflow are clocking differences.  What is your reference clock source?  Is this shared with the FPGA?

    Thanks,

    Drew