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TLK10232: Auto-negotiation link establishment issue at 1G speed

Part Number: TLK10232

Hello,

We have used TLK10232 dual phy device for a XAUI to SFP/SFP+ application and we have a problem in 1G link establishment when auto-negotiation is enabled.

The initialization of the device is shown below:

  • Reset device (assert RESET_N pin)
  • Select the reference clock selection (312.5 MHz)
  • Disable auto-negotiation
  • Disable link training
  • Write 16’h03FF to 0x1E.8020
  • Write HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101
  • Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3
  • Enable auto-negotiation 0x07.0000 bit 12 ->1'b1
  • Issue AN_RESTART (0x07.0000 bit 9 ->1'b1
  • Read AN_CONTROL register to clear AN_RESTART bit

The peer device is a VIAVI MTS5800 Tester configured at speed=1G, auto-negotiation=on.

The inventory info of the SFPs used at both the tester & the PHY (TLK10232)  side are:

Inventory:

Identifier : 0x03 (SFP)
Extended identifier : 0x04 (GBIC/SFP defined by 2-wire interface ID)
Connector : 0x07 (LC)
Transceiver codes : 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
10G Ethernet Compliance Codes: 10G Base-LR
Ethernet Compliance Codes: -
Fibre Channel Link Length: -
Fibre Channel Technology: -
SFP+ Cable Technology: -
Fibre Channel Transmission Media: -
Fibre Channel Speed: -
Encoding : 0x06
BR, Nominal : 10300 MBd
Rate identifier : 0x00 (unspecified)
Length (SMF,km) : 10km
Length (SMF) : 10000m
Length (50um) : 0m
Length (62.5um) : 0m
Length (Copper) : 0m
Length (OM3) : 0m
Laser wavelength : 1310nm
Vendor name : FIBRAIN
Vendor OUI : 00:1b:c5
Vendor PN : FTFS1XGS31L010DI
Vendor rev : 1.0
Option values : 0x1a
Option : RX_LOS implemented
Option : TX_FAULT implemented
Option : TX_DISABLE implemented
BR margin, max : 0%
BR margin, min : 0%
Vendor SN : CIC20210034
Date code : 2020-05-14


Checking the AN_STATUS register  (0x07.0001) the value is 0x88 (AN_COMLETE=0, LINK_STATUS=0)

The tester also indicates link down.

When I tried to do an AN_RESET (reg. 0x070000 bit 15->1'b1) then the link to the PHY side came up but the link at the tester side was still down.

Checking the AN_STATUS register (0x070001) the value is 0xac (AN_COMPLETE=1, LINK_STATUS=1), AN_BP_STATUS (0x070030) value  is 0x3 (AN_1G_KX=1).

Can you provide us some info how to proceed?

Thanks in advance,

Panayotis