TUSB1104: TUSB1104: Enabling USB 3.2 Gen 2 x2 (20Gbps) not working (continue thread)

Dharrvindra V Parthepan

Part Number: TUSB1104

Hi David Liu,

Sorry for the late reply as was working on other projects.
Below is the previous thread.
TUSB1104: Enabling USB 3.2 Gen 2 x2 (20Gbps) not working - Interface forum - Interface - TI E2E support forums

Below is the measurement I have collected.

CH1: pin09_SSTX2+

CH2: pin16_SSTX1+

CH3: pin40_CTX2+

CH4: pin33_CTX1+

FLIP pin

Default BIOS (Set as USB3.2 Gen2 x1)

3.3V

AllPairedBIOS (Set as Paired in xml)

3.3V

over 1 year ago

0 David (ASIC) Liu over 1 year ago

TI__Guru**** 160696 points

Dharrvin

Did you get a chance to probe the termination on TX1/2 and RX1/2 on both sides of TUSB1104 using a multimeter? When TUSB1104 powers up and sees termination on both TX1/RX1 and TX2/RX2, it will be in USB3.2 Gen 2 x 2 mode with CONFIG/Non-CONFIG lane determined by the FLIP driven by the PD controller.

Thanks

David

0 Dharrvindra V Parthepan over 1 year ago in reply to David (ASIC) Liu

Prodigy 20 points

Hi David,
I have did measurements using two BIOS settings.
One is set as USB3.2 Gen 2 x1 and another setting is called as paired.

1. Default BIOS is set as USB3.2 Gen2x1.

CH1: pin09_SSTX2+

CH2: pin16_SSTX1+

CH3: pin40_CTX2+

CH4: pin33_CTX1+

As you can see there is activity on SSTX2+ and CTX2+ in above measurements screenshot but not for SSTX1+ and CTX1+ as expected to use 1 pair of USB3.2 TX and RX. I had only measured the TX1 and TX2 on both sides using active probe. For flip pin, I had currently measured using multimeter as the oscilloscope only has 4 Channel to measure the TX1/2 on both sides.

2.AllPairedBIOS (Set as Paired in xml)

CH1: pin09_SSTX2+

CH2: pin16_SSTX1+

CH3: pin40_CTX2+

CH4: pin33_CTX1+

As you can see there is activity no activity on SSTX2+ and SSTX1+ and the CTX1+ and CTX2+ stays at 800+mV in above measurements screenshot.

The flip pin for above measurement stays at 3.3V as well.
For both setup im using Kingston XS2000 without changing its insertion orientation. Isn't the Flip pin is supposed to indicate the direction of insertion of the device to Type-C port?

0 David (ASIC) Liu over 1 year ago in reply to Dharrvindra V Parthepan

TI__Guru**** 160696 points

HI,

When TUSB1104 powers up and sees termination on both TX1/RX1 and TX2/RX2, it will be in USB3.2 Gen 2 x 2 mode with CONFIG/Non-CONFIG lane determined by the FLIP driven by the PD controller. So instead using the scope, can you use a multimeter to check for the termination first? My worry is that when the BIOS is in USB3.2 Gen2 x 2, it is not enabling its termination on both RX1 and RX2.

Thanks

David

0 Dharrvindra V Parthepan over 1 year ago in reply to David (ASIC) Liu

Prodigy 20 points

Hi David,
Here is the measurement I had collected using multimeter (voltage and resistance to GND with both BIOS). Did I measure correctly?
Based on observation that SSRX1/SSRX2 is open, CTX1 is open, CTX2 is in MegaOhm value most likely open too.

Pin	Pin Name	Resistance measurement to GND using default BIOS	Voltage measurement to GND using default BIOS	Resistance measurement to GND using AllPaired BIOS (USB3.2 Gen2x2)	Voltage measurement to GND using AllPaired BIOS (USB3.2 Gen2x2)
9	SSTX2+	106kOhm	0V	86.3Ohm	11mV
10	SSTX2-	106kOhm	0V	85.9Ohm	11mV
12	SSRX2+	Open	0V	Open	854mV
13	SSRX2-	Open	0V	Open	855mV
16	SSTX1+	70Ohm	0V	83Ohm	10mV
15	SSTX-	70Ohm	0V	83Ohm	10mV
19	SSRX1+	Open	860mV	Open	860mV
18	SSRX1-	Open	850mV	Open	850mV

40	CTX2+	Open	0V	42.78MOhm	802mV
39	CTX2-	Open	0V	43.3MOhm	804mV
37	CRX2+	101kOhm	0V	79.2Ohm	10mV
36	CRX2-	101kOhm	0V	79Ohm	10mV
33	CTX1+	Open	830mV	Open	831mV
34	CTX1-	Open	820mV	Open	838mV
30	CRX1+	60Ohm	0V	65.9Ohm	6mV
31	CRX1-	60Ohm	0V	67Ohm	6mV

Thank you.
Best Regards,
Dharrvin

0 David (ASIC) Liu over 1 year ago in reply to Dharrvindra V Parthepan

TI__Guru**** 160696 points

Dharrvin

Looking at your schematic, just want to check on the AC coupling capacitors, do you have the capacitors populated as shown below?

The table does seem to show the TUSB1104 termination is being enabled on both lanes. So if you probe both lanes, are you seeing LFPS being sent on TX and RX for both lanes?

Thanks

David

0 Dharrvindra V Parthepan over 1 year ago in reply to David (ASIC) Liu

Prodigy 20 points

Hi David,

Module PCH side(100nF on SSTX1 and SSTX2) -> COM-HPC connector -> TUSB1104I (0R on SSTX and 220nF SSRX) -> Type-C connector (220nF on CTX1&CTX2, 330nF on CRX1&CRX2)

Module (PCH side)

Module (COM-HPC connector)

Carrier (COM-HPC connector)

Carrier (TUSB1104I)

Type-C Connector

There is no LFPS pattern observed.
Do you need a screenshot for startup from G3 to S0 indicating there is no LFPS pattern?
Do we need to change from 100nF to 220nF for SSTX1 and SSTX2?
Below I'm attaching pdf of overview USB connection from module to carrier via COM-HPC connector.
CCAS-DEV-SCM-C1-0-rev10_USB.pdf
ADHC_S111_B0_RC2_USB2.pdf

Thank you.

Best Regards,

Dharrvin

0 David (ASIC) Liu over 1 year ago in reply to Dharrvindra V Parthepan

TI__Guru**** 160696 points

Dharrvin

You can use either 100nF or 220nF for SSTX1 and SSTX2.

Does the FLIP pin change its voltage for the normal and flip Type-C orientation? You should see 0V on FLIP pin for the normal orientation and 3.3V for the flip orientation.

For USB3.2 Gen2 x 2, one lane will be used as a configure lane and the other lane will be used as an un-configured lane depending on the Type-C orientation. Lane 1 will be the configure lane for the normal orientation and lane 2 will the configure lane for the flip orientation. How does the PCH know which one is configured in this case?

Thanks

David