DS90UB935-Q1: Static electricity test issue

Hi Hale,

Can you provide more details on what specific changes you have made that did not work? 

• Is the system is properly shielded?
• Do you have a TVS protection diode in the FPD-Link line?
• If you monitor the voltage rails during the ESD test, do they move outside the allowed VDD range? 

In terms of software, can you try setting Reg 0x05 PAR_ERR_THOLD_HI to 0xFF and Reg 0x06 PAR_ERR_THOLD_LO to 0xFF?  If that does not work, disable RX_PARITY_CHECKER_EN.

Regards,

Cindy

Cindy,

Thanks for your support.

The previous link is https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1237654/ds90ub935-q1-the-esd-test-failed?tisearch=e2e-sitesearch&keymatch=ESD#

And the schematic is sent to your email. Do you have any TVS part number to recommend? The customer replied that the TVS function influence is little to optimize the issue.

Hi Hale,

Our device pins have internal ESD protection, so the external ESD diode is optional. Some characteristics to keep in mind is making sure the diodes have low line capacitance, good IEC-61000-4-2 ratings, and low clamping voltages. Also make sure that the VRWM voltage is at the appropriate rating, depending on whether you put it before or after the AC coupling capacitor on the DOUT+ pin. One example is TPD1E01B04-Q1. 

Regards,

Cindy

Cindy,

About the register, I didn't find the related information. Could you point out where we can find related information and why we need to modify the register.

Cindy Li said:

In terms of software, can you try setting Reg 0x05 PAR_ERR_THOLD_HI to 0xFF and Reg 0x06 PAR_ERR_THOLD_LO to 0xFF?  If that does not work, disable RX_PARITY_CHECKER_EN.

Hi Hale,

These registers are located in the deserializer. Are you using the DS90UB936 deserializer? 

By default, the AEQ in the DES will check for FPD3 errors including parity errors. If enough errors are detected, the AEQ will re-adapt which causes a re-lock of the devices. This can interrupt the video stream. Increasing the parity error threshold can help mitigate this if the ESD events are causing parity errors.

Another HW check is to make sure all enclosures and connectors are properly grounded. It is recommended to use a case that optimizes the space to minimize the air gap and ensuring there are multiple ground points.

Regards,

Cindy

Hi Cindy,

Thanks for your help.

I let the customer test the VDD and the test waveform is as below. It seems that the voltage is large when the power-on start. And the customer actually find the other party to help check that the schematic design including TVS/ESD design. It seems no issue. Do you know how to reduce the peak? Any suggestion to help reduce the peak?

About your suggestion to modify the software, the customer also tried, but it seems no use. So about the software, do you have any suggestion or any other register to modify?

Cindy Li said:

In terms of software, can you try setting Reg 0x05 PAR_ERR_THOLD_HI to 0xFF and Reg 0x06 PAR_ERR_THOLD_LO to 0xFF?  If that does not work, disable RX_PARITY_CHECKER_EN.

Hi Hale,

Is the voltage you measured the one going into the VDD18 pin? Is the voltage not meeting the device power pin specifications? I am having difficulty reading your screenshots. 

Just to confirm, is LOCK dropping when you have these ESD events? 

The only other software suggestions are the same ones that were suggested in the E2E you linked, which you say did not fix your issue. I would double check the hardware if the software optimizations are not working. It could be layout/shielding related. 

Regards,

Cindy

Cindy,

Thanks for your support. And I will share the schematic and the software later via e-mail.

Hi Hale,

I can review the schematic and scripts and provide feedback in 1-2 business days. 

Regards,

Cindy

Hi Hale,

Below are my comments on the 935 schematic: 

• I noticed that pin 25 VDDD has the ferrite bead placed between the two decoupling capacitors. It should be placed right after the 1.8V supply to follow the Typical Application Diagram. 
• The decoupling scheme for VDDPLL_CAP is different from the datasheet. Ensure that the supply pin specifications from Section 6.3 Recommended Operating Conditions are met (measured directly at the pin).
• The ferrite bead should be 1kOhm@100MHz, but the schematic uses 120Ohm@100MHz. Ensure that the supply pin specifications are met.

If the supply pin specifications move outside the allowed VDD range during ESD testing, you can try to add filter caps.

Regards,

Cindy

Thanks, Cindy.

Could you also please check the PCB layout and script? I will send the script later.

Sorry for the mistake.

The script had been sent to you. I will send the PCB layout to you later.

Hi Cindy,

And according to your advice, the display also has stuck and stopped when there is EMC test with disable the RX_PARITY_CHECKER_EN.

Cindy Li said:

If that does not work, disable RX_PARITY_CHECKER_EN.

Hi Hale,

I will look over the layout and provide feedback in 1-2 business days.

For the scripts, I responded via email since they mention an NDA deserializer. If you want to ask questions about it on E2E, feel free to start a new thread on the Interface Internal forum and we can continue there.

Regards,

Cindy

Hi Hale,

I looked over the layout and sent you my feedback via email. 

Regards,

Cindy