• State Resolved
  • Locked Locked
  • Replies 10 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 373 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65LVPE501

curb frank
Prodigy 30 points
Other Parts Discussed in Thread: SN65LVPE501

We use the redriver chip SN65LVPE501 in the PCIE link. Currently, there is a phenomenon that cannot be identified. Do you have any recommended reference design?

  • +1
    TI__Guru* 91440 points

    Hi Curb:

    Please send us your schematic so we can review. I am assuming this is PCIe Gen1 or 2.

    Regards, Nasser

  • +1 in reply to Nasser Mohammadi
    Prodigy 30 points

    The left circuit is the sending end (connecting the host), the right circuit is the receiving end (connecting the slave), and they are connected by a coaxial cable

  • 0 in reply to curb frank
    TI__Genius 11065 points

    Hi Curb,

    Based on your schematic and consulting Table 2 in the datasheet, it looks like the device is configured with the following settings:

    • Output amplitude: 1100 mVpp
    • De-emphasis: -6.6 dB
    • Equalization: 7 dB at PCIe Gen 2 speed
    • RX detection: enabled
    • Power saving: disabled

    If you are having problems forming a PCIe link, it may be helpful to reduce the de-emphasis and equalization to the minimum values (float the OS and EQ pins) and run the system at PCIe Gen 1 speeds to see if there is a difference.

    However it is difficult to say much with the provided information. Can you tell us more about what the problem is and what generation of PCIe the system is running at?

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 30 points

    • We use PCIE gen1 on WINdows10。

    • In addition, we found that it is necessary to set RX_END to 0 to establish a link. If RX_END is set to 1 as you said, the link cannot establish a connection.
  • 0 in reply to curb frank
    TI__Genius 11065 points

    Hi Curb,

    curb frank said:
    In addition, we found that it is necessary to set RX_END to 0 to establish a link. If RX_END is set to 1 as you said, the link cannot establish a connection.

    To be clear, is this unusual behavior of EN_RXD the problem you are experiencing?

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 30 points

    If we use two SN65LVPE501 chips for concatenation in order to increase transmission distance, do the parameters of the two channels need to be set to the same?

    An SN65LVPE501 chip can be transmitted at PCIE GEN1 speed by adjusting the parameters of how far the distance can be transmitted

    Thanks so much！
  • 0 in reply to Evan Su
    Prodigy 30 points

    We use a SN65LVPE501 chip loopback test to see the effect of the eye map. Could you please help us see which eye map is in line with the requirements?

  • +1 in reply to curb frank
    TI__Genius 11065 points

    Hi Curb,

    curb frank said:
    If we use two SN65LVPE501 chips for concatenation in order to increase transmission distance, do the parameters of the two channels need to be set to the same?

    We generally do not recommend cascading PCIe redrivers for several reasons:

    • Each redriver in series adds random jitter
    • Difficult to tune, combined transfer function of multiple redrivers can drive signal outside of linear range if not careful

    It can still be done but we do not have any advice regarding the implementation.

    curb frank said:

    An SN65LVPE501 chip can be transmitted at PCIE GEN1 speed by adjusting the parameters of how far the distance can be transmitted

    Thanks so much！

    I cannot find exact figures, but the first page of the datasheet says it can compensate for 30 inches of 6 mil Stripline on FR4. The graphs on pages 14-16 show the results for up to 44 inches of trace length at PCIe Gen 2 speeds.

    curb frank said:
    We use a SN65LVPE501 chip loopback test to see the effect of the eye map. Could you please help us see which eye map is in line with the requirements?

    I have not been able to find the exact eye requirements for PCIe Gen 1, but I expect the minimum eye width requirement to be close to 0.3 UI. This eye map suggests that the eye width is about 0.7 UI, which should be fine.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 30 points

    We connect PCIE signals on the host end and slave end using coaxial line. The host end enters the receiving end of SN65LVPE501 chip through the coaxial line, and then connects the slave device through the coaxial line from the sending end of the chip. How far can the transmission distance be supported？

    Thank you!

  • 0 in reply to curb frank
    TI__Genius 11065 points

    Hi Curb,

    The maximum transmission distance will depend on the insertion loss characteristics of your coaxial cable. As I mentioned, the datasheet shows the device can extend up to 44 inches of traces at PCIe Gen 2 speeds. Assuming these traces are FR4, which has around 0.6 dB/in of insertion loss at a Nyquist frequency of 4 GHz, then 44 inches translates to a rough estimate of 27 dB total loss. At Gen 1 speeds the boost may be somewhat lower but I have no specific data on that.

    Best,

    Evan Su