Other Parts Discussed in Thread: DS92LV3242, , SN75LVDS83B, DS90C189-Q1
I am working on a design that interfaces to the LVDS interface (not LVCMOS) of the DS92LV3241/DS92LV3242. I've found this design guide which details at a high level that a PRBS and DC balancing scheme are used for data encoding: https://www.ti.com/lit/ug/snla200/snla200.pdf?ts=1696554380509&ref_url=https%253A%252F%252Fwww.google.com%252F
Can you share more detail regarding the PRBS, bit scrambling, and DC balancing? We'd like to be able to eliminate half of the SerDes hardware by embedding the LVDS scheme into our FPGA due to tight space constraints.