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DS92LV3241: PRBS, bit scrambling, and DC balancing

Klaus Ulander
Prodigy 20 points
Part Number: DS92LV3241
Other Parts Discussed in Thread: DS92LV3242, , SN75LVDS83B, DS90C189-Q1

I am working on a design that interfaces to the LVDS interface (not LVCMOS) of the DS92LV3241/DS92LV3242.  I've found this design guide which details at a high level that a PRBS and DC balancing scheme are used for data encoding: https://www.ti.com/lit/ug/snla200/snla200.pdf?ts=1696554380509&ref_url=https%253A%252F%252Fwww.google.com%252F

Can you share more detail regarding the PRBS, bit scrambling, and DC balancing?  We'd like to be able to eliminate half of the SerDes hardware by embedding the LVDS scheme into our FPGA due to tight space constraints.  

  • 0
    TI__Mastermind 18120 points

    Hi Klaus,

    The encoding of the channel link devices is proprietary, so I cannot give details on bit scrambling or DC balancing. I can see if there is a better device to fit your needs if I have more information on your system. 

    Is your primary need to bridge LVCMOS to LVDS?

    Best,

    Jack

  • 0
    Prodigy 20 points

    Hi Jack, thanks for following up.  Our primary need is to reduce I/O to the FPGA.  The DS92LV3241/DS92LV3242 look to be an attractive Serdes option, that breaks I/O 32 down to 8 (4 differential).  This I/O reduction is critical to our system architecture with selected FPGA and available I/O to interface to a variety of payloads.  If we could absorb half the SerDes interface into the FPGA we could eliminate half the hardware of the SerDes chain.  This reduction in hardware would allow us to meet our design requirements within our space constraints.  So it's not quite a bridge LVCMOS to LVDS need, as much as it is a reduce I/O and capitalize on SerDes HW in order to expand I/O on an existing design.


  • 0 in reply to Klaus Ulander
    TI__Mastermind 18120 points

    Hi Klaus,

    Devices such as the DS90C189-Q1 and the SN75LVDS83B serialize the data without adding encoding or scrambling. The LVDS/oLDI format is open-standard so an FPGA could be programmed to deserialize these signals.

    Best,

    Jack 

  • 0 in reply to Jack Scherlag
    Prodigy 20 points

    Thanks Jack.  I'll take a look.  Although not as fast as the DS92LV3421/2, these devices sound simpler to implement an I/O expansion scheme.  Thanks for the help!