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TCA9535: Calculations on using the TCA9535 pull-up resistor

SHENG YANG
Expert 1090 points
Part Number: TCA9535

HI.experts

The project is planned to be designed using the TCA9535 and is expected to use 8 TCA9535s.I read the technical manual (SLVA689).There are some questions in the documentation, please help with them.

1、How is the value of bus capacitance Cb determined in the manual?

2、In SLVA689 fSCL=100kHZ,Tr=1us,fSCL=400kHZ,Tr=300ns,if fSCL is other frequency how to determine the value of Tr? For example, fSCL=10kHZ, Tr is equal to?

3、If I use 8 TCA9535s, is it ok to use 1 pull-up resistor each for SDA and SCL? Or do I need to use more than one pull-up resistor? What is the proper placement of the pull-up resistors when performing PCBLAOUT?

thank you.

  • 0
    Guru 244360 points

    1. You can estimate it with about 10 pF per device, and 1 pF per cm of trace. If in doubt, look at the waveforms with an oscilloscope.

    2. These values are requires by the I²C specification for standard mode and fast mode. For clocks slower than 100 kHz in standard mode or slower than 400 kHz in fast mode, you should simply use the same rise time.

    3. Each bus segment should have its own pull-up resistor. The placement does not matter.

  • 0
    TI__Mastermind 23943 points

    Hi Sheng,

    SHENG YANG said:
    How is the value of bus capacitance Cb determined in the manual?

    As Clemens mentioned, Cb is determined as a summation of input capacitance and trace capacitance. 

    Each master/slave device connected to the I2C bus is estimated to have roughly 10pF of input capacitance. IF you have 1 master and 9 slave devices, this would result in 100pF of input capacitance on the I2C bus alone, excluding trace cap. 

    PCB trace capacitance can be estimated like Clemens stated: 1pF/cm, or 3pF/inch are estimations used to determine the total parasitic capacitance from a trace. 

    These two totals will help determine a total Cb that can be used in calculation. If you decide go off the maximum Cb, you can pull this information from the I2C standard depending on which data rate you are using. i.e. 400pF (max) for standard mode and fast mode.

    SHENG YANG said:
    2、In SLVA689 fSCL=100kHZ,Tr=1us,fSCL=400kHZ,Tr=300ns,if fSCL is other frequency how to determine the value of Tr? For example, fSCL=10kHZ, Tr is equal to?

    I2C standard provides the maximum rise time allowed for a specific data rate. If the speed like you stated is less than the maximum speed of the I2C mode (fSCL = 10kHz) then you can use the rise time of standard mode (1us) in calculation. 

    SHENG YANG said:
    3、If I use 8 TCA9535s, is it ok to use 1 pull-up resistor each for SDA and SCL? Or do I need to use more than one pull-up resistor? What is the proper placement of the pull-up resistors when performing PCBLAOUT?

    1 pull-up resistor is probably ideal to keep the application simple and save on PCB space. Like Clemens stated, each bus segment should have its own pull-up resistor and the placement doe not matter. If all 8 TCA9535's are connected to a single bus segment, 1 pull-up resistor is sufficient. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Expert 1090 points

    HI.Tyler Townsend.

    Thank you very much for your support .

    1、I have one more question in response to the above response, please help confirm. The second question is about Tr. If it is less than 100KHZ, then 1uS is used, if it is more than 400KHZ, then 300ns is used, and if 100KHZ<fCLK<400KHZ, then how should Tr be determined?

    2、If I follow the formula below to calculate the maximum and minimum resistance values, fCLK = 400KHZ, Cb = 400PF, VCC = 5V, Vol (max) = 0.4V, IoL = 3mA, Tr = 300ns, calculated Rp (max) = 885Ω, Rp (min) = 966.667Ω, the maximum value than the minimum value of the smaller. How to understand this?

    3、In response to the third question, for example, if I use 1 MCU and 8 TCA9535s for IIC communication, and the TCA9535s are labeled 1~8, if 1 is closest to the MCU and 8 is farthest away from the MCU, then it is OK to place the pull-up resistors for SDA and SCL anywhere on the IIC bus at the time of PCBLAYOUT? No need to consider the location from MCU is?

    4、I need to consider a small resistor in series with the line from SDA, SCL? Something like 33Ω, 22Ω, 100Ω.

  • 0 in reply to SHENG YANG
    Guru 244360 points

    1. For all clocks up to 100 kHz, you can use 1 µs. For all clocks up to 400 kHz, you can use 300 ns.

    2. It means that you cannot use 3 mA with a 400 pF bus. For such extreme cases, the I²C specification allows 6 mA at VOL ≤ 0.6 V for fast mode; if your devices cannot support this, then you cannot use 400 kHz. (In practice, your bus will not have such a large capacitance.)

    3. Electrically, master and slaves behave the same. The pull-up resistor can be anywhere.

    4. There might be reasons to add such a resistor, but in most cases, it is not needed. It would increase VOL, so it should not be too large (< about 47 Ω).

  • 0 in reply to Clemens Ladisch
    Expert 1090 points

    HI.Clemens 

    Thank you very much for your support .

    For reply 1 above, I can understand that Tr=1uS for less than 400KHZ, and Tr=300nS for more than 400KHZ is this the understanding?

    I currently have an IIC using hardware between an MCU and an EEPROM, the PCB wiring SDA and SCL are each about 3cm long, with layer swaps and punched holes in the middle of the line. According to the manual（SLVA689）, the capacitance of the two chips is 20PF, the line is 3PF according to 3cm, and there are three vias on the line, each of which is calculated according to 10PF, with Cb=53PF. However, when I look at it through the oscilloscope, I can see that I need to use a pull-up resistor of about 2.7K to meet the requirement when Fclk=100KHZ and Tr=1uF. According to the curve provided in the manual this is exactly the value of the resistor at Cb=400PF, this is confusing me. Can you help answer why?

    Can you give some advice on layout and wiring for IIC in terms of LAYOUT?

  • 0 in reply to SHENG YANG
    Guru 244360 points

    Standard-mode I²C allows all frequencies between 0 Hz and 100 kHz, and rise times between 0 µs and 1 µs.
    Fast-mode I²C allows all frequencies between 0 Hz and 400 kHz, and rise times between 20 ns and 300 ns.
    You must not go above 400 kHz.

    The rise time must be measured between the I²C switching thresholds, i.e., between 30 % and 70 % of VCC.

  • +1 in reply to SHENG YANG
    TI__Mastermind 23943 points

    Hi Sheng,

    To answer/add onto previous questions:

    SHENG YANG said:
    1、I have one more question in response to the above response, please help confirm. The second question is about Tr. If it is less than 100KHZ, then 1uS is used, if it is more than 400KHZ, then 300ns is used, and if 100KHZ<fCLK<400KHZ, then how should Tr be determined?

    As Clemens has stated, for the 100kHz < fCLK < 400kHz, use Tr = 300ns. 

    SHENG YANG said:
    2、If I follow the formula below to calculate the maximum and minimum resistance values, fCLK = 400KHZ, Cb = 400PF, VCC = 5V, Vol (max) = 0.4V, IoL = 3mA, Tr = 300ns, calculated Rp (max) = 885Ω, Rp (min) = 966.667Ω, the maximum value than the minimum value of the smaller. How to understand this?

    The mismatch of Rp(max) = 885 ohm and Rp(min) = 966.667 ohm shows an incapability of the I2C device. 

    The minimum calculation takes into account the supply voltage VCC, IOL, and VOL. An I2C standardized device is suppose to be able to sink 3mA of current at an output low voltage of 0.4V. If you find that your Rp(min) > Rp(max), then either the drive strength of the I2C device needs to strengthen or the overall supply voltage would need to be lowered. 

    For example, a VCC = 5V is much slower to rise to from a GND state than it is to rise to a VCC = 3.3V. It takes significantly less time, therefore, a system change of supply voltage might be necessary if the slave device cannot increase the drive strength to what Clemens has mentioned (6mA, VOL < 0.6V). 

    SHENG YANG said:
    3、In response to the third question, for example, if I use 1 MCU and 8 TCA9535s for IIC communication, and the TCA9535s are labeled 1~8, if 1 is closest to the MCU and 8 is farthest away from the MCU, then it is OK to place the pull-up resistors for SDA and SCL anywhere on the IIC bus at the time of PCBLAYOUT? No need to consider the location from MCU is?

    Because the data rate of I2C is so slow, there is no need to recommend specific placement of the pull-up resistor. We don't care about reflections in this case since I2C is a single ended open drain protocol that does not drive a high logic state but instead idles the bus, and the pull-up resistor pulls the voltage of the I2C bus segment to a logic high voltage. Placement of the pull-up resistor does not matter. 

    SHENG YANG said:
    4、I need to consider a small resistor in series with the line from SDA, SCL? Something like 33Ω, 22Ω, 100Ω.

    Like CLemens previously stated, adding in series resistance increases the VOL since a current flows through the resistance and creates a voltage drop when the I2C bus is driven low. 22ohm, 33ohm, or 100ohm could be potential series resistor solutions as long as you don't violate the VIL(max) of the bus (30% of VCC). 

    Adding series resistance is usually only required if your system is experiencing harsh overshoots when driving the I2C bus LOW. The negative spikes during an overshoot could potentially damage a device depending on its abs. maximum negative input voltage to the SDA / SCL lines. 

    SHENG YANG said:
    For reply 1 above, I can understand that Tr=1uS for less than 400KHZ, and Tr=300nS for more than 400KHZ is this the understanding?

    This is not correct understanding. Please use the rise-times below for the modes specified by the I2C standard. 

    0kHz < fSCL < 100kHz, Tr = 1uS (1000ns) (standard mode)

    100kHz < fSCL < 400kHz, Tr = 300ns (fast mode) 

    SHENG YANG said:
    I currently have an IIC using hardware between an MCU and an EEPROM, the PCB wiring SDA and SCL are each about 3cm long, with layer swaps and punched holes in the middle of the line. According to the manual（SLVA689）, the capacitance of the two chips is 20PF, the line is 3PF according to 3cm, and there are three vias on the line, each of which is calculated according to 10PF, with Cb=53PF. However, when I look at it through the oscilloscope, I can see that I need to use a pull-up resistor of about 2.7K to meet the requirement when Fclk=100KHZ and Tr=1uF. According to the curve provided in the manual this is exactly the value of the resistor at Cb=400PF, this is confusing me. Can you help answer why?

    Like Clemens stated, rise-time is the time it takes for a signal to rise from 30% of VCC to 70% of VCC. 10% to 90% is not correct rise-time estimation in I2C if you are measuring it that way. 

    Also, your summation of bus capacitance is an estimated calculation of total bus capacitance and may not be exact. 

    capacitance of two chips is 20pF, 1pF/cm of trace, but in your previous comments you have 8 TCA9535's in your system. The input cap is 3pF/device typ, but could be a maximum of 8pF / device. The additional capacitance of vias may or may not be accurate as well. Also, the width of the PCB traces may add/subtract to the total Cb. 

    Please show a scope capture of how you are measuring the rise-time. 

    SHENG YANG said:
    Can you give some advice on layout and wiring for IIC in terms of LAYOUT?

    In general, I usually recommend to keep traces short and concise with few bends as possible. THe longer traces add more parasitic bus cap (Cb). 

    I try to keep the I2C bus on the same layer, if you have to add vias, this adds more inductance to wires increases overshoots and ringing. Also adds cap as well to the system. 

    Try to keep the I2C bus from noisy sources on the PCB. I.e. if you have a motor driver on the bus, it might be best to route the I2C bus away from the device to prevent excess noise from coupling onto the I2C bus lines. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Expert 1090 points

    HI.Tyler Townsend.

    Thank you very much for your support .

    If Tr is following 30%VCC~70%VCC, then I'm starting to misunderstand. I understood it as 10%~90%.

    The example I mentioned above is an IIC solution I'm currently using for IIC communication between the MCU and the EEPROM.

    The following figure shows the IIC communication waveform between MCU and EEPROM. The waveform at fclk=100KHZ, VCC=5V, yellow for SDA, green for SCL.

    So if you use fCLK=100KHZ,Tr according to 30%VCC~70%VCC to meet between less than 1uS is to comply with the requirements of the regulations, so the understanding of the right?

    Subsequent projects will use one MCU and 8 TCA9535 for the project design, I predicted that the IIC will need about 30cm of wiring, should I be able to meet the requirements without the IIC repeater?

  • 0 in reply to SHENG YANG
    TI__Mastermind 23943 points

    Hi Sheng,

    SHENG YANG said:
    Subsequent projects will use one MCU and 8 TCA9535 for the project design, I predicted that the IIC will need about 30cm of wiring, should I be able to meet the requirements without the IIC repeater?

    It is hard for me to say for sure, its dependent on the amount of capacitance the wiring would add to the system. The datasheet for the type of wire should give an estimate pF/length measurement to estimate the total capacitance of the wire. 

    On the scope, the signals look ok. I think you would find a better rise-time measurement if you used small resolution step size. In the last scope shot provided, this is not a correct way to measure rise-time. Please see the rise-time figure below from the I2C standard. 

    This is a more accurate depiction of how rise time is measured in I2C. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Expert 1090 points

    HI.Tyler Townsend.

    Thank you very much for your support .

    “The datasheet for the type of wire should give an estimate pF/length measurement to estimate the total capacitance of the wire“. 

    Which of the datasheets answered above has a description of the requirements for this wiring specification?

  • 0 in reply to SHENG YANG
    TI__Mastermind 23943 points

    Hi Sheng,

    SHENG YANG said:
    Which of the datasheets answered above has a description of the requirements for this wiring specification?

    I am talking about a datasheet specific to the type of wire you are using. Not a datasheet specific to the IC. The datasheet I am referring to is something you would have access to on your end. 

    If it is something simple like a jumper wire, then estimate a few pF/Inch of wire, but ultimately, o-scope captures would help to show if you are within I2C standards. 

    Regards,

    Tyler