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DS90UB953-Q1: SDA output clarifications

David Shumate
Expert 7225 points
Part Number: DS90UB953-Q1

Hi Team,

Could I get your help supporting some questions on I2C bus configuration/timing for the 953:

  1. Please provide more definition on the following fields in the I2C_CONTROL2 register and what they affect:
    1. SDA_OUTPUT_SETUP
    2. SDA_OUTPUT_DELAY
  2. I can’t find a timing diagram that includes variables defining the Min/Max I2C SDA output skew relative to SCL.  The diagram below seems to only include the SDA input requirements to the serializer I2C interface.

Best,

David

  • 0
    TI__Mastermind 22960 points

    Hi David,

    Thank you for your questions. 

    1. These registers are used to fine tune the behavior of the I2C controller within the 953. In most applications these registers should be left as the default values since the I2C behavior of the 953 (or any FPD-Link device) is compliant with the standard I2C protocol. The only time these would need to be programmed is if there is a system level issue that would require more fine tuning. The I2C standard does specify these timing specs according to the mode being used (standard, fast mode, or fast mode plus) so if these settings do need to be modified, care needs to be taken to ensure that there are no violations. If any timing violations do occur, the I2C communication would likely fail and/or contain errors.
      1. The SDA setup time is referring to the amount of time the SDA line remains stable prior to sampling or a start/stop condition. This is sometimes referred to as Tsu in diagrams.
      2. The SDA output delay controls when the 953 will begin to drive the SDA line low after the SCL goes low. The device monitors the external SCL line and will detect the falling edge. When the falling edge is detected, the 953 will wait the programmed delay time and then drive the SDA line accordingly.

    2. Could you clarify  "the Min/Max I2C SDA output skew relative to SCL"? The I2C protocol does specify setup and hold times, which relate to the overall timing of the lines and would indirectly impact the skew.

    Regards,
    Darrah

  • 0 in reply to Darrah Merillat
    TI__Expert 7225 points

    Thanks for the response Darrah, from my understanding the serializer will change the state of the SDA 240 ns after SCL goes low.  The 240ns comes from the default value in the SDA_OUTPUT_DELAY field of the I2C_CONTROL2 register.  It is my understanding that the delay specified in this register is a nominal value.  What is the tolerance?

    We are using Fast mode and the register value is configured to SDA_OUTPUT_DELAY value is configured to 240 ns and SDA_OUTPUT_SETUP is also set to default of “1”. Could you please help us understand if this needs a change? Our registers 0x0B and 0x0C are set to 0x13 and 0x26.

  • 0 in reply to David Shumate
    TI__Mastermind 22960 points

    Hi David,

    Your understanding is correct, and we only have the nominal values of the SDA_OUTPUT_DELAY available. However, these register settings should not need any modifications for I2C communication to function as expected.