TFP401A-Q1: Output timings values

Johnson John

Part Number: TFP401A-Q1
Other Parts Discussed in Thread: TFP401A, TFP401

Hello TI team,

Can you please clarify output timing parameters of TFP401A device.

We saw that output setup and hold time values are given in table 7.7 and Figure 8-4 datasheet. We want to interface the output signals of TFP401 device with our LVDS serializer chip timings.

If you look at the Figure 8-4 in the datasheet, output clock "ODCK" changes with reference to data output (RGB). Our question is, how do you interpret the datasheet timing values for the output timing parameters?

Could you please clarify when does the output data (RGB) change with reference to clock output signal? If we set "OCK_INV" = High, Do I need to set rising edge sampling or falling edge sampling in my serializer chip to meet timing parameters?

thank you,

Johnson John

9 months ago

0 Zach Dryer 9 months ago

TI__Genius 13290 points

Hello, Johnson,

I am looking into this now and will get back to you shortly.

Thanks,

Zach

0 Zach Dryer 9 months ago in reply to Zach Dryer

TI__Genius 13290 points

Hello, Johnson,

When you say Figure 8-4 I assume you meant Figure 6-4 showing the setup times and the hold times of the clock.

The set-up and hold times are proportional to the pixel clock, the lower the frequency the longer the set-up time.
It is NOT recommended to use different clock edge latching , if you select rising-edge on the RGB receiver you should select it on the TFP as well.

The ODCK polarity selects ODCK edge to which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC, VSYNC, DE, CTL[3:1]) latch. If selected to be high, this latches output data on rising ODCK edge. If low, Latches output data on falling ODCK edge.

I found another thread here that you can reference:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/590406/tfp401a-q1-tfp401a-q1-maximum-setup-time

Thanks,
Zach

0 Johnson John 9 months ago in reply to Zach Dryer

Intellectual 620 points

Hi Zach,

thank you for the response! and the link!

Can you please clarify:

Our device full part#TFP401AIPZPRQ1

To ensure my understanding, I have drawn the output data w.r.t to ODCK below (165MHz), and mentioned timing values as per the datasheet.

Yes, I clearly understand from your response and the link, the setup time will increase with lower clock frequency. Our concern is on the Hold time requirement margin.

When we set the rising edge for TFT401AI and RGB receiver then I am getting minimum guaranteed hold time of 0.3ns from the TFT401AI device, Correct, please confirm?

Our RGB receiver device "THC63LVD827-Z" requires minimum 0.8ns Hold timing requirement, looks like we could not meet it. Could you check whether our understanding is fine? anything we do to get positive hold timing margin?

thank you for the help, appreciated,

Johnson John

0 Zach Dryer 9 months ago in reply to Johnson John

TI__Genius 13290 points

Hello,

Assuming that your test conditions are 1 pixels per clock, PIXS = low, OCK_INV = high then:

2.1 ns is your min. setup time from start of valid data to beginning of rising clock edge.

0.3 ns is your min. hold time from end of rising clock edge to end valid data.

Does your RGB receiver support 2-pixels-per-clock input mode? From the datasheet the min hold time becomes greater if PIXS = High.

Thanks,

Zach

0 Johnson John 9 months ago in reply to Zach Dryer

Intellectual 620 points

Hi Zach,

thank you for confirming our understanding.

Unfortunately the RGB receiver "THC63LVD827-Z" does not support 2pixel/clk input mode (Supports Double edge input only).

So, Do you have any options, like Staggering mode or reducing clock frequency (If yes what is clock frequency) or any options to meet hold time requirement?

Appreciated your help!

Johnson John

0 Zach Dryer 9 months ago in reply to Johnson John

TI__Genius 13290 points

Hello,

The staggered pixel select is an active-low signal used in the 2-pixels-per-clock pixel mode (PIXS = high).

Please allow me to check internally on any data that we may have that could help and will reach back out to you tomorrow.

Thanks,

Zach

+1 Zach Dryer 9 months ago in reply to Zach Dryer

TI__Genius 13290 points

Hello, Johnson,

I could not find any data that indicates any other options to meet hold time requirement.

Thanks,

Zach

0 Johnson John 9 months ago in reply to Zach Dryer

Intellectual 620 points

Hi Zach,

thank you for the support! appreciated!

regards,

Johnson John

0 Zach Dryer 9 months ago in reply to Johnson John

TI__Genius 13290 points

Hello, Johnson,

You are welcome!

Thanks,

Zach

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TFP401A-Q1: Output timings values