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Hello team
We'd like to make sure about configuration to achieve customer required operation.
They'd like to transmit LVDS CLK during Lock=low.
Is suppose that we can achieve this condition by
Is this understanding correct?
Best regards,
Kazuki Kuramochi
Hi Shu,
I have additional question.
We found following description in datasheet.
8.3.13 Oscillator Output
The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost.
This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable)
Does it mean we need to configure 0x02 bit 5:Auto Clock Enable =1?
Best regards,
Kazuki Kuramochi
Hi Kuramochi-san,
This is correct. The OSC clock output will need to be enabled 0x2[5] = '1' if the customer wishes to have TxCLKOUT output when the input clock is lost.
Best.
Shu
Hi Shu-san,
Thank you for your reply and I understand.
Best regards,
Kazuki Kuramochi