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DS90UH928Q-Q1: Using LVDS CLK output during Lock=L

Part Number: DS90UH928Q-Q1

Hello team

We'd like to make sure about configuration to achieve customer required operation.

They'd like to transmit LVDS CLK during Lock=low.
Is suppose that we can achieve this condition by

  1. 0x02 bit6(OEN/OSS_SEL) = 1
  2. 0x02 bit4(OSS_SEL) = 1

Is this understanding correct?

Best regards,
Kazuki Kuramochi