Hi Team,
Do we have any data or insight on the propagation delay that this Diff Line Receiver has over temperature, load and process variation?
My customer is trying to get repeatable prop delays, so any insight here is appreciated. They are open to alternative recommendations in the same footprint, if that enables them to have more repeatable prop delay across devices.
Thanks,
JP
Hi JP,
So this part has a propagation delay, both tPHL and tPLH, of min: 8ns; typical: 16ns; max: 26ns with the following test setup:
So a load of 15pF.
We don't take data at other loads for propagation delay - so the load is constant for our data. That being said - more output capacitance will decrease propagation delay. Our test setup is trying to minimize loading's impact on prop delay so we are measuring device performance and not focusing on RC charging constant from load. Since it is measuring the 50% to 50% point - the output's rise time is dictated by the loading capacitance and output resistance. In our test setup we minimize capacitive loading so that we can measure silicon performance. However if you increase the capacitive load the charge time from 0% to 50% increases proportionally to increase of capacitance - i.e. if you double output load your rise time increases by double - which will increase your propagation delay as the charge time to 50% increases.
In general higher temperature is going to slow down the device as well because output impedance increases with temperature.
As for predictable propagation delays - it will be in the range specified 8ns to 26ns if your load capacitance is 15pF or lower (generally speaking - the 50% charge time should be about 1.5ns - so pretty small - but the output impedance can dramatically change that) - I don't really think I will be able to give you much better times - as in all reality when I was going through approximating output impedance - on this device it varies from 20 Ohms to 1k ohms depending on usage case (highest exists at lowest VCC and highest temperature with low output current (-100uA)).
There really won't be a better performing part in terms of propagation delay variability - the skew between HL and LH transitions is capped to 6ns (could be longer with more output capacitance) on this device - so while the range is large there won't be a lot of skew associated with it. Generally speaking we try to tell customers that as long as maximum propagation delay and pulse max pulse skew is okay within system it shouldn't be a big issue how variable it is. However the lower the output capacitance the better results you will generally see as well.
This may not be as helpful as they are looking for - but we don't have much data to support the request. Essentially higher temperature and lower VCC will increase propagation delays where higher VCC and lower temperature decrease propagation delays because silicon is less resistive in colder temperatures and more resistive in hotter ones.
Please let me know if there are any other questions!
Best,
Parker Dodson
