Dear expert,
For UB941 (external ref clock)+UB948 system, does it support SoC to stop video and then resume?
Thanks
Hi Ryan,
What specific UB941, 948 registers need re-program for video stop/resume?
On the UB941, the DSI and DPHY error registers will need to be cleared when video starts up again as video stopping could cause DSI/DPHY errors.
Once the SoC enters sleep mode (if the DSI outputs are not left in LP-11 or escape mode), the DSI inputs on the UB941 need to be disabled (0x01[3] = 1). Once the DSI output is active again on the SoC, the DSI inputs can be reactivated (0x01[3] = 0).
On the 948 when video stops, the LVDS output will need to be disabled to make sure that random video output isn't displayed (0x2[7] = 1). Once video returns from the SoC, the device will need a digital reset after enabling LVDS output (0x02[7] = 1 then 0x01[0] = 1).
948 datasheet
Best,
Jack
Jack,
Only 1 system among 5 system under test shows this problem after every 500~1000 times test.
But this system doesn't show this problem without this new procedure change.
Below is good video:
Below is bad video. Color become strange.
When problem happen,
1. Digital Reset 941 cannot recover problem.
2. Digital Reset 948 can recover problem.
3. Switch to 941 color bar, still show problem
4. Switch to 948 color bar, still show problem
5. Switch to MCU color bar, problem is gone (MCU is between 988 and panel)
Do you have any suggestion?
