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DS25CP104A: EN_smb

ttd
Mastermind 7900 points
Part Number: DS25CP104A

Dear Technical Support Team,

What is the timing of EN_smb?

Question 1:
What is the minimum pulse width when used as a Reset signal?
Question 2:
What is the minimum wait time until SMBus communication becomes available after setting Low->High?

We are planning to use the following flow
　1. instruct FPGA to execute Reset on DS25CP104
　2. the FPGA asserts EN_smb Low and initializes the DS25CP104 registers
　3. return EN_smb to High
　4. transfer various initial settings to DS25CP104 via SMBus

Question 1 is Low pulse width from 2 to 3,
Question 2 assumes a wait time from 3 to 4

Best Regards,

ttd

  • 0
    TI__Guru* 93290 points

    Greetings,

    1). This parameter has not been characterized. Having said this, given bus free time between stop and start is 4.7uS, this means device state machine is able to recognize this delay and respond to the SMBus commands. Because of this, the thinking is that minimum EN_smb is 4.7uS - at least.

    2). Typically wait time is in order of 16ms. This is based on discussion with one of the digital designers.

    Regards, Nasser