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DS90CF366: LVDS receiver timing

Wenjun Tao
Prodigy 80 points
Part Number: DS90CF366

Hi TI,

I am calculating LVDS receiver timing for DS90CF366 based on snla249.pdf method, and want to confirm the meaning of Rspos and how clk cycle to cycle jitter impact Rspos.

  • from the wording, Rspos0 define the absolute min and max position of strobe, e.g. for bit0, Rspos0_min=0.49ns, Rspos0_max=1.19ns, Rspos0_typ=0.84ns, the max-min window=1.19-0.49=0.7ns
  • if cycle to cycle jitter move the typical strobe position to 0.54ns, will the Rspos0_min and Rspon0_max move to 0.19ns and 0.89ns respectively (just keep the window to be 0.7ns is ok?)? Or Rspos0_min and Rspos0_max still keep 0.49ns and 1.19ns?

thanks

wenjun

  • 0
    TI__Guru** 103215 points

    Hello Wenjun,

    Due to the US public holiday, our team is currently out of office and will return tomorrow. Thank you for your patience during this time 

    Best Regards,

    Casey 

  • 0
    TI__Genius 9330 points

    Hi Wenjun,

    The Rspos_max and Rspos_min can be calculated by using the equations 1 and 2 in page 5 of the app note.

    Wenjun Tao said:
    if cycle to cycle jitter move the typical strobe position to 0.54ns, will the Rspos0_min and Rspon0_max move to 0.19ns and 0.89ns respectively (just keep the window to be 0.7ns is ok?)? Or Rspos0_min and Rspos0_max still keep 0.49ns and 1.19ns?

    It still has the min and max as 0.49ns and 1.19ns.

    Best Regards,

    Gil Abarca

  • 0 in reply to Gil Abarca Ramos
    Prodigy 80 points

    Hi Gil,

    Thanks for your reply!

    In other words, I hope know how clk cycle to cycle jitter impact left/right bit margin of equation1/2 in app note.

    • In my opinion, clk cycle to cycle jitter will impact Rspos_min/max position, then further impact the left/right bit margin, I am not sure if my opinion is right, and need confirm with you.

    thanks

    wenjun

  • 0 in reply to Wenjun Tao
    TI__Genius 9330 points

    Hi Wenjun,

    The Rspos_min/max is not impacted by the clk cycle to cycle jitter. If there is clk cycle to cycle jitter the min and max rspos remain the same that is stated in the Switching Characteristics table with a frequency of 85MHz. 

    The clock cycle to cycle jitter would impact the RSKM value:

    Best Regards,

    Gil Abarca