Thanks for your previous answer.
We have tested to access to the PHY after a 3µs RESET low pulse from all possible MDIO addresses but the PHY does not answer at any MDIO address.
More precisely, the PHY_ADD strap pins are connected as below:
RX_D0 : not used pin, left open (i.e. no pull-up/ no pull-down)
RX_D2 : connected to FPGA Microsemi Polarfire input through 100nF serial capacitor, used for differential SGMII data output (without pull-up/down).
So MODE 1 is wished to be selected for RX_D0 and RX_D2.
But I wonder if there is a unstable level of SGMII signal during the short reset (3µs), due to the discharge of equivalent RC device (serial 100nF, 9kR pull-down internal PHY). Practically, this is solved by increasing the reset to 3ms (duration x1000 for testing).
What do you think ? What is the PHY pin strap configuration if the RS_D2 voltage is changing during reset ?
What would you recommend ? Did you experience projetcs with PHY reset pulse much larger than 3µs (a few ms) ?
Many thanks.
Emmanuel
